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https://github.com/cemu-project/Cemu.git
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Refactor more GX2 code to use LatteReg.h
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Exzap
parent
96800c6f97
commit
524188bb7a
10 changed files with 536 additions and 262 deletions
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@ -8,204 +8,6 @@
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#include "GX2.h"
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#include "GX2_Shader.h"
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void gx2Export_GX2SetFetchShader(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetFetchShader(0x{:08x})", hCPU->gpr[3]);
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GX2ReserveCmdSpace(11);
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GX2FetchShader_t* fetchShaderPtr = (GX2FetchShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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cemu_assert_debug((_swapEndianU32(fetchShaderPtr->shaderPtr) & 0xFF) == 0);
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gx2WriteGather_submit(
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// setup fetch shader
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pm4HeaderType3(IT_SET_CONTEXT_REG, 1+5),
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mmSQ_PGM_START_FS-0xA000,
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_swapEndianU32(fetchShaderPtr->shaderPtr)>>8, // pointer divided by 256
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_swapEndianU32(fetchShaderPtr->shaderSize)>>3, // size divided by 8
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0x10000, // ukn (ring buffer size?)
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0x10000, // ukn (ring buffer size?)
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*(uint32be*)&(fetchShaderPtr->_regs[0]),
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// write instance step
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pm4HeaderType3(IT_SET_CONTEXT_REG, 1+2),
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mmVGT_INSTANCE_STEP_RATE_0-0xA000,
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*(uint32be*)&(fetchShaderPtr->divisors[0]),
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*(uint32be*)&(fetchShaderPtr->divisors[1]));
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osLib_returnFromFunction(hCPU, 0);
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}
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void gx2Export_GX2GetVertexShaderGPRs(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2GetVertexShaderGPRs(0x{:08x})", hCPU->gpr[3]);
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GX2VertexShader_t* vertexShader = (GX2VertexShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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uint8 numGPRs = _swapEndianU32(vertexShader->regs[0])&0xFF;
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osLib_returnFromFunction(hCPU, numGPRs);
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}
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void gx2Export_GX2GetVertexShaderStackEntries(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2GetVertexShaderStackEntries(0x{:08x})", hCPU->gpr[3]);
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GX2VertexShader_t* vertexShader = (GX2VertexShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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uint8 stackEntries = (_swapEndianU32(vertexShader->regs[0])>>8)&0xFF;
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osLib_returnFromFunction(hCPU, stackEntries);
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}
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void gx2Export_GX2GetPixelShaderGPRs(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2GetPixelShaderGPRs(0x{:08x})", hCPU->gpr[3]);
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GX2PixelShader_t* pixelShader = (GX2PixelShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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uint8 stackEntries = (_swapEndianU32(pixelShader->regs[0]))&0xFF;
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osLib_returnFromFunction(hCPU, stackEntries);
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}
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void gx2Export_GX2GetPixelShaderStackEntries(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2GetPixelShaderStackEntries(0x{:08x})", hCPU->gpr[3]);
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GX2PixelShader_t* pixelShader = (GX2PixelShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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uint8 numGPRs = (_swapEndianU32(pixelShader->regs[0]>>8))&0xFF;
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osLib_returnFromFunction(hCPU, numGPRs);
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}
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void gx2Export_GX2SetVertexShader(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetVertexShader(0x{:08x})", hCPU->gpr[3]);
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GX2ReserveCmdSpace(100);
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GX2VertexShader_t* vertexShader = (GX2VertexShader_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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MPTR shaderProgramAddr;
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uint32 shaderProgramSize;
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if( _swapEndianU32(vertexShader->shaderPtr) != MPTR_NULL )
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{
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// without R API
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shaderProgramAddr = _swapEndianU32(vertexShader->shaderPtr);
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shaderProgramSize = _swapEndianU32(vertexShader->shaderSize);
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}
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else
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{
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shaderProgramAddr = vertexShader->rBuffer.GetVirtualAddr();
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shaderProgramSize = vertexShader->rBuffer.GetSize();
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}
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cemu_assert_debug(shaderProgramAddr != 0);
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cemu_assert_debug(shaderProgramSize != 0);
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if( _swapEndianU32(vertexShader->shaderMode) == GX2_SHADER_MODE_GEOMETRY_SHADER )
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{
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// in geometry shader mode the vertex shader is written to _ES register and almost all vs control registers are set by GX2SetGeometryShader
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 6));
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gx2WriteGather_submitU32AsBE(mmSQ_PGM_START_ES-0xA000);
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gx2WriteGather_submitU32AsBE(memory_virtualToPhysical(shaderProgramAddr)>>8);
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gx2WriteGather_submitU32AsBE(shaderProgramSize>>3);
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gx2WriteGather_submitU32AsBE(0x100000);
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gx2WriteGather_submitU32AsBE(0x100000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->regs[0])); // unknown
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}
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else
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{
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gx2WriteGather_submit(
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/* vertex shader program */
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pm4HeaderType3(IT_SET_CONTEXT_REG, 6),
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mmSQ_PGM_START_VS-0xA000,
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memory_virtualToPhysical(shaderProgramAddr)>>8, // physical address
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shaderProgramSize>>3, // size
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0x100000,
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0x100000,
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_swapEndianU32(vertexShader->regs[0]), // unknown
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/* primitive id enable */
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pm4HeaderType3(IT_SET_CONTEXT_REG, 2),
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mmVGT_PRIMITIVEID_EN-0xA000,
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_swapEndianU32(vertexShader->regs[1]),
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/* output config */
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pm4HeaderType3(IT_SET_CONTEXT_REG, 2),
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mmSPI_VS_OUT_CONFIG-0xA000,
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_swapEndianU32(vertexShader->regs[2]));
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if( (_swapEndianU32(vertexShader->regs[2]) & 1) != 0 )
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debugBreakpoint(); // per-component flag?
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// ukn
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 2));
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gx2WriteGather_submitU32AsBE(mmPA_CL_VS_OUT_CNTL-0xA000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->regs[14]));
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uint32 numOutputIds = _swapEndianU32(vertexShader->regs[3]);
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numOutputIds = std::min<uint32>(numOutputIds, 0xA);
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+numOutputIds));
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gx2WriteGather_submitU32AsBE(mmSPI_VS_OUT_ID_0-0xA000);
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for(uint32 i=0; i<numOutputIds; i++)
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{
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->regs[4+i]));
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}
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/*
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VS _regs[]:
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0 ?
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1 mmVGT_PRIMITIVEID_EN (?)
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2 mmSPI_VS_OUT_CONFIG
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3 Number of used SPI_VS_OUT_ID_* entries
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4 - 13 SPI_VS_OUT_ID_0 - SPI_VS_OUT_ID_9
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14 pa_cl_vs_out_cntl
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...
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17 - ?? semantic table entry (input)
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...
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50 vgt_vertex_reuse_block_cntl
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51 vgt_hos_reuse_depth
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*/
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// todo: mmSQ_PGM_CF_OFFSET_VS
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// todo: mmVGT_STRMOUT_BUFFER_EN
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// stream out
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if( _swapEndianU32(vertexShader->usesStreamOut) != 0 )
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{
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// stride 0
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 2));
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gx2WriteGather_submitU32AsBE(mmVGT_STRMOUT_VTX_STRIDE_0-0xA000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->streamOutVertexStride[0])>>2);
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// stride 1
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 2));
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gx2WriteGather_submitU32AsBE(mmVGT_STRMOUT_VTX_STRIDE_1-0xA000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->streamOutVertexStride[1])>>2);
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// stride 2
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 2));
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gx2WriteGather_submitU32AsBE(mmVGT_STRMOUT_VTX_STRIDE_2-0xA000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->streamOutVertexStride[2])>>2);
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// stride 3
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 2));
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gx2WriteGather_submitU32AsBE(mmVGT_STRMOUT_VTX_STRIDE_3-0xA000);
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gx2WriteGather_submitU32AsBE(_swapEndianU32(vertexShader->streamOutVertexStride[3])>>2);
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}
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}
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// update semantic table
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uint32 vsSemanticTableSize = _swapEndianU32(vertexShader->regs[0x40/4]);
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if( vsSemanticTableSize > 0 )
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{
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+1));
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gx2WriteGather_submitU32AsBE(mmSQ_VTX_SEMANTIC_CLEAR-0xA000);
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gx2WriteGather_submitU32AsBE(0xFFFFFFFF);
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if( vsSemanticTableSize == 0 )
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{
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// todo: Figure out how this is done on real SW/HW (some vertex shaders don't have a semantic table)
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+1));
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gx2WriteGather_submitU32AsBE(mmSQ_VTX_SEMANTIC_0-0xA000);
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gx2WriteGather_submitU32AsBE(0xFFFFFFFF);
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}
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else
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{
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uint32* vsSemanticTable = vertexShader->regs+(0x44/4);
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vsSemanticTableSize = std::min<uint32>(vsSemanticTableSize, 0x20);
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+vsSemanticTableSize));
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gx2WriteGather_submitU32AsBE(mmSQ_VTX_SEMANTIC_0-0xA000);
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for(uint32 i=0; i<vsSemanticTableSize; i++)
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gx2WriteGather_submitU32AsLE(vsSemanticTable[i]);
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}
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}
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osLib_returnFromFunction(hCPU, 0);
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}
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void gx2Export_GX2SetPixelShader(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetPixelShader(0x{:08x})", hCPU->gpr[3]);
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@ -415,14 +217,14 @@ void gx2Export_GX2SetGeometryShader(PPCInterpreter_t* hCPU)
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osLib_returnFromFunction(hCPU, 0);
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}
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struct GX2ComputeShader_t
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struct GX2ComputeShader
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{
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/* +0x00 */ uint32be regs[12];
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/* +0x30 */ uint32be programSize;
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/* +0x34 */ uint32be programPtr;
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/* +0x38 */ uint32 ukn38;
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/* +0x3C */ uint32 ukn3C;
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/* +0x40 */ uint32 ukn40[8];
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/* +0x38 */ uint32be ukn38;
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/* +0x3C */ uint32be ukn3C;
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/* +0x40 */ uint32be ukn40[8];
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/* +0x60 */ uint32be workgroupSizeX;
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/* +0x64 */ uint32be workgroupSizeY;
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/* +0x68 */ uint32be workgroupSizeZ;
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@ -431,13 +233,13 @@ struct GX2ComputeShader_t
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/* +0x74 */ GX2RBuffer rBuffer;
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};
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static_assert(offsetof(GX2ComputeShader_t, programSize) == 0x30);
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static_assert(offsetof(GX2ComputeShader_t, workgroupSizeX) == 0x60);
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static_assert(offsetof(GX2ComputeShader_t, rBuffer) == 0x74);
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static_assert(offsetof(GX2ComputeShader, programSize) == 0x30);
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static_assert(offsetof(GX2ComputeShader, workgroupSizeX) == 0x60);
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static_assert(offsetof(GX2ComputeShader, rBuffer) == 0x74);
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void gx2Export_GX2SetComputeShader(PPCInterpreter_t* hCPU)
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{
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ppcDefineParamTypePtr(computeShader, GX2ComputeShader_t, 0);
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ppcDefineParamTypePtr(computeShader, GX2ComputeShader, 0);
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cemuLog_log(LogType::GX2, "GX2SetComputeShader(0x{:08x})", hCPU->gpr[3]);
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MPTR shaderPtr;
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