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PPCRec: Smaller cleanups
This commit is contained in:
parent
3031a98b16
commit
4f4caaaa73
7 changed files with 41 additions and 55 deletions
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@ -1204,16 +1204,11 @@ void PPCRecompilerX64Gen_imlInstruction_r_name(PPCRecFunction_t* PPCRecFunction,
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else if (imlInstruction->op_r_name.regR.GetBaseFormat() == IMLRegFormat::F64)
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else if (imlInstruction->op_r_name.regR.GetBaseFormat() == IMLRegFormat::F64)
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{
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{
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auto regR = _regF64(imlInstruction->op_r_name.regR);
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auto regR = _regF64(imlInstruction->op_r_name.regR);
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if (name >= PPCREC_NAME_FPR0 && name < (PPCREC_NAME_FPR0 + 32))
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if (name >= PPCREC_NAME_FPR_HALF && name < (PPCREC_NAME_FPR_HALF + 64))
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{
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{
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x64Gen_movupd_xmmReg_memReg128(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * (name - PPCREC_NAME_FPR0));
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sint32 regIndex = (name - PPCREC_NAME_FPR_HALF) / 2;
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}
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sint32 pairIndex = (name - PPCREC_NAME_FPR_HALF) % 2;
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else if (name >= PPCREC_NAME_FPR0_NEW && name < (PPCREC_NAME_FPR0_NEW + 64))
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x64Gen_movsd_xmmReg_memReg64(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * regIndex + pairIndex * sizeof(double));
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{
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sint32 regIndex = (name - PPCREC_NAME_FPR0_NEW) / 2;
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sint32 pairIndex = (name - PPCREC_NAME_FPR0_NEW) % 2;
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x64Gen_movddup_xmmReg_memReg64(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * regIndex + pairIndex * sizeof(double));
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// todo - use movsd here
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}
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}
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else if (name >= PPCREC_NAME_TEMPORARY_FPR0 || name < (PPCREC_NAME_TEMPORARY_FPR0 + 8))
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else if (name >= PPCREC_NAME_TEMPORARY_FPR0 || name < (PPCREC_NAME_TEMPORARY_FPR0 + 8))
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{
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{
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@ -1288,14 +1283,10 @@ void PPCRecompilerX64Gen_imlInstruction_name_r(PPCRecFunction_t* PPCRecFunction,
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{
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{
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auto regR = _regF64(imlInstruction->op_r_name.regR);
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auto regR = _regF64(imlInstruction->op_r_name.regR);
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uint32 name = imlInstruction->op_r_name.name;
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uint32 name = imlInstruction->op_r_name.name;
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if (name >= PPCREC_NAME_FPR0 && name < (PPCREC_NAME_FPR0 + 32))
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if (name >= PPCREC_NAME_FPR_HALF && name < (PPCREC_NAME_FPR_HALF + 64))
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{
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{
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x64Gen_movupd_memReg128_xmmReg(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * (name - PPCREC_NAME_FPR0));
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sint32 regIndex = (name - PPCREC_NAME_FPR_HALF) / 2;
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}
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sint32 pairIndex = (name - PPCREC_NAME_FPR_HALF) % 2;
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else if (name >= PPCREC_NAME_FPR0_NEW && name < (PPCREC_NAME_FPR0_NEW + 64))
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{
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sint32 regIndex = (name - PPCREC_NAME_FPR0_NEW) / 2;
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sint32 pairIndex = (name - PPCREC_NAME_FPR0_NEW) % 2;
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x64Gen_movsd_memReg64_xmmReg(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * regIndex + (pairIndex ? sizeof(double) : 0));
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x64Gen_movsd_memReg64_xmmReg(x64GenContext, regR, REG_RESV_HCPU, offsetof(PPCInterpreter_t, fpr) + sizeof(FPR_t) * regIndex + (pairIndex ? sizeof(double) : 0));
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}
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}
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else if (name >= PPCREC_NAME_TEMPORARY_FPR0 && name < (PPCREC_NAME_TEMPORARY_FPR0 + 8))
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else if (name >= PPCREC_NAME_TEMPORARY_FPR0 && name < (PPCREC_NAME_TEMPORARY_FPR0 + 8))
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@ -42,7 +42,7 @@ bool PPCRecompilerX64Gen_imlInstruction_fpr_load(PPCRecFunction_t* PPCRecFunctio
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realRegisterMem2 = _regI32(imlInstruction->op_storeLoad.registerMem2);
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realRegisterMem2 = _regI32(imlInstruction->op_storeLoad.registerMem2);
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uint8 mode = imlInstruction->op_storeLoad.mode;
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uint8 mode = imlInstruction->op_storeLoad.mode;
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if( mode == PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0 )
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if( mode == PPCREC_FPR_LD_MODE_SINGLE )
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{
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{
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// load byte swapped single into temporary FPR
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// load byte swapped single into temporary FPR
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if( indexed )
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if( indexed )
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@ -74,7 +74,7 @@ bool PPCRecompilerX64Gen_imlInstruction_fpr_load(PPCRecFunction_t* PPCRecFunctio
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x64Gen_cvtss2sd_xmmReg_xmmReg(x64GenContext, realRegisterXMM, realRegisterXMM);
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x64Gen_cvtss2sd_xmmReg_xmmReg(x64GenContext, realRegisterXMM, realRegisterXMM);
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}
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}
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}
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}
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else if( mode == PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0 )
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else if( mode == PPCREC_FPR_LD_MODE_DOUBLE )
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{
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{
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if( g_CPUFeatures.x86.avx )
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if( g_CPUFeatures.x86.avx )
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{
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{
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@ -149,7 +149,7 @@ bool PPCRecompilerX64Gen_imlInstruction_fpr_store(PPCRecFunction_t* PPCRecFuncti
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if( indexed )
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if( indexed )
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realRegisterMem2 = _regI32(imlInstruction->op_storeLoad.registerMem2);
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realRegisterMem2 = _regI32(imlInstruction->op_storeLoad.registerMem2);
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uint8 mode = imlInstruction->op_storeLoad.mode;
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uint8 mode = imlInstruction->op_storeLoad.mode;
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if( mode == PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0 )
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if( mode == PPCREC_FPR_ST_MODE_SINGLE )
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{
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{
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if (imlInstruction->op_storeLoad.flags2.notExpanded)
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if (imlInstruction->op_storeLoad.flags2.notExpanded)
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{
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{
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@ -178,7 +178,7 @@ bool PPCRecompilerX64Gen_imlInstruction_fpr_store(PPCRecFunction_t* PPCRecFuncti
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x64Gen_sub_reg64Low32_reg64Low32(x64GenContext, realRegisterMem, realRegisterMem2);
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x64Gen_sub_reg64Low32_reg64Low32(x64GenContext, realRegisterMem, realRegisterMem2);
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}
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}
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}
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}
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else if( mode == PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0 )
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else if( mode == PPCREC_FPR_ST_MODE_DOUBLE )
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{
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{
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if( indexed )
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if( indexed )
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{
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{
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@ -189,14 +189,10 @@ void IMLDebug_DisassembleInstruction(const IMLInstruction& inst, std::string& di
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{
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{
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strOutput.addFmt("r{}", inst.op_r_name.name - PPCREC_NAME_R0);
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strOutput.addFmt("r{}", inst.op_r_name.name - PPCREC_NAME_R0);
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}
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_FPR0 && inst.op_r_name.name < (PPCREC_NAME_FPR0 + 32))
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if (inst.op_r_name.name >= PPCREC_NAME_FPR_HALF && inst.op_r_name.name < (PPCREC_NAME_FPR_HALF + 32*2))
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{
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{
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strOutput.addFmt("f{}", inst.op_r_name.name - PPCREC_NAME_FPR0);
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strOutput.addFmt("f{}", inst.op_r_name.name - ((PPCREC_NAME_FPR_HALF - inst.op_r_name.name)/2));
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}
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if ((inst.op_r_name.name-PPCREC_NAME_FPR_HALF)&1)
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else if (inst.op_r_name.name >= PPCREC_NAME_FPR0_NEW && inst.op_r_name.name < (PPCREC_NAME_FPR0_NEW + 32*2))
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{
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strOutput.addFmt("f{}", inst.op_r_name.name - ((PPCREC_NAME_FPR0_NEW - inst.op_r_name.name)/2));
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if ((inst.op_r_name.name-PPCREC_NAME_FPR0_NEW)&1)
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strOutput.add(".ps1");
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strOutput.add(".ps1");
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else
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else
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strOutput.add(".ps0");
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strOutput.add(".ps0");
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@ -229,11 +229,11 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
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// determine partially written result
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// determine partially written result
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switch (op_storeLoad.mode)
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switch (op_storeLoad.mode)
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{
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{
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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case PPCREC_FPR_LD_MODE_DOUBLE:
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// PS1 remains the same
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// PS1 remains the same
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registersUsed->readGPR2 = op_storeLoad.registerData;
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registersUsed->readGPR2 = op_storeLoad.registerData;
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break;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0:
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case PPCREC_FPR_LD_MODE_SINGLE:
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break;
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break;
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default:
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default:
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cemu_assert_unimplemented();
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cemu_assert_unimplemented();
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@ -251,11 +251,11 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
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// determine partially written result
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// determine partially written result
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switch (op_storeLoad.mode)
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switch (op_storeLoad.mode)
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{
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{
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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case PPCREC_FPR_LD_MODE_DOUBLE:
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// PS1 remains the same
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// PS1 remains the same
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registersUsed->readGPR3 = op_storeLoad.registerData;
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registersUsed->readGPR3 = op_storeLoad.registerData;
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break;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0:
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case PPCREC_FPR_LD_MODE_SINGLE:
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break;
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break;
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default:
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default:
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cemu_assert_unimplemented();
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cemu_assert_unimplemented();
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@ -251,8 +251,7 @@ enum // IMLName
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PPCREC_NAME_TEMPORARY = 1000,
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PPCREC_NAME_TEMPORARY = 1000,
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PPCREC_NAME_R0 = 2000,
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PPCREC_NAME_R0 = 2000,
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PPCREC_NAME_SPR0 = 3000,
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PPCREC_NAME_SPR0 = 3000,
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PPCREC_NAME_FPR0 = 4000,
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PPCREC_NAME_FPR_HALF = 4800, // Counts PS0 and PS1 separately. E.g. fp3.ps1 is at offset 3 * 2 + 1
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PPCREC_NAME_FPR0_NEW = 4800, // similar to FPR0, but counting PS0 and PS1 separate. So fp3.ps1 is at offset 3 * 2 + 1
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PPCREC_NAME_TEMPORARY_FPR0 = 5000, // 0 to 7
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PPCREC_NAME_TEMPORARY_FPR0 = 5000, // 0 to 7
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PPCREC_NAME_XER_CA = 6000, // carry bit from XER
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PPCREC_NAME_XER_CA = 6000, // carry bit from XER
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PPCREC_NAME_XER_OV = 6001, // overflow bit from XER
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PPCREC_NAME_XER_OV = 6001, // overflow bit from XER
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@ -268,12 +267,12 @@ enum // IMLName
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enum
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enum
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{
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{
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// fpr load
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// fpr load
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PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_SINGLE,
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PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_DOUBLE,
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// fpr store
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// fpr store
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PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, // store 1 single precision float from ps0
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PPCREC_FPR_ST_MODE_SINGLE,
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PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0, // store 1 double precision float from ps0
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PPCREC_FPR_ST_MODE_DOUBLE,
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PPCREC_FPR_ST_MODE_UI32_FROM_PS0, // store raw low-32bit of PS0
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PPCREC_FPR_ST_MODE_UI32_FROM_PS0, // store raw low-32bit of PS0
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};
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};
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@ -34,8 +34,8 @@ void PPCRecompiler_optimizeDirectFloatCopiesScanForward(ppcImlGenContext_t* ppcI
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if (imlInstruction->IsSuffixInstruction())
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if (imlInstruction->IsSuffixInstruction())
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break;
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break;
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// check if FPR is stored
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// check if FPR is stored
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if ((imlInstruction->type == PPCREC_IML_TYPE_FPR_STORE && imlInstruction->op_storeLoad.mode == PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0) ||
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if ((imlInstruction->type == PPCREC_IML_TYPE_FPR_STORE && imlInstruction->op_storeLoad.mode == PPCREC_FPR_ST_MODE_SINGLE) ||
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(imlInstruction->type == PPCREC_IML_TYPE_FPR_STORE_INDEXED && imlInstruction->op_storeLoad.mode == PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0))
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(imlInstruction->type == PPCREC_IML_TYPE_FPR_STORE_INDEXED && imlInstruction->op_storeLoad.mode == PPCREC_FPR_ST_MODE_SINGLE))
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{
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{
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if (imlInstruction->op_storeLoad.registerData.GetRegID() == fprIndex)
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if (imlInstruction->op_storeLoad.registerData.GetRegID() == fprIndex)
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{
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{
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@ -18,13 +18,13 @@ IMLReg _GetRegCR(ppcImlGenContext_t* ppcImlGenContext, uint8 crReg, uint8 crBit)
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IMLReg _GetFPRRegPS0(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex)
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IMLReg _GetFPRRegPS0(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex)
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{
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{
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cemu_assert_debug(regIndex < 32);
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cemu_assert_debug(regIndex < 32);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR0_NEW + regIndex * 2 + 0, IMLRegFormat::F64);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR_HALF + regIndex * 2 + 0, IMLRegFormat::F64);
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}
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}
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IMLReg _GetFPRRegPS1(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex)
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IMLReg _GetFPRRegPS1(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex)
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{
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{
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cemu_assert_debug(regIndex < 32);
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cemu_assert_debug(regIndex < 32);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR0_NEW + regIndex * 2 + 1, IMLRegFormat::F64);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR_HALF + regIndex * 2 + 1, IMLRegFormat::F64);
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}
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}
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IMLReg _GetFPRTemp(ppcImlGenContext_t* ppcImlGenContext, uint32 index)
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IMLReg _GetFPRTemp(ppcImlGenContext_t* ppcImlGenContext, uint32 index)
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@ -36,7 +36,7 @@ IMLReg _GetFPRTemp(ppcImlGenContext_t* ppcImlGenContext, uint32 index)
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IMLReg _GetFPRReg(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex, bool selectPS1)
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IMLReg _GetFPRReg(ppcImlGenContext_t* ppcImlGenContext, uint32 regIndex, bool selectPS1)
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{
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{
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cemu_assert_debug(regIndex < 32);
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cemu_assert_debug(regIndex < 32);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR0_NEW + regIndex * 2 + (selectPS1 ? 1 : 0), IMLRegFormat::F64);
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return PPCRecompilerImlGen_LookupReg(ppcImlGenContext, PPCREC_NAME_FPR_HALF + regIndex * 2 + (selectPS1 ? 1 : 0), IMLRegFormat::F64);
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}
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}
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/*
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/*
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@ -66,12 +66,12 @@ bool PPCRecompilerImlGen_LFS_LFSU_LFD_LFDU(ppcImlGenContext_t* ppcImlGenContext,
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if (isDouble)
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if (isDouble)
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{
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{
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// LFD/LFDU
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// LFD/LFDU
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister, imm, PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister, imm, PPCREC_FPR_LD_MODE_DOUBLE, true);
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}
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}
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else
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else
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{
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{
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// LFS/LFSU
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// LFS/LFSU
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister, imm, PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister, imm, PPCREC_FPR_LD_MODE_SINGLE, true);
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if( ppcImlGenContext->LSQE )
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if( ppcImlGenContext->LSQE )
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{
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{
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DefinePS1(fpPs1, frD);
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DefinePS1(fpPs1, frD);
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@ -99,16 +99,16 @@ bool PPCRecompilerImlGen_LFSX_LFSUX_LFDX_LFDUX(ppcImlGenContext_t* ppcImlGenCont
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if (isDouble)
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if (isDouble)
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{
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{
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if (withUpdate)
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if (withUpdate)
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister1, 0, PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory(fpPs0, gprRegister1, 0, PPCREC_FPR_LD_MODE_DOUBLE, true);
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else
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else
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ppcImlGenContext->emitInst().make_fpr_r_memory_indexed(fpPs0, gprRegister1, gprRegister2, PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory_indexed(fpPs0, gprRegister1, gprRegister2, PPCREC_FPR_LD_MODE_DOUBLE, true);
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}
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}
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else
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else
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{
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{
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if (withUpdate)
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if (withUpdate)
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ppcImlGenContext->emitInst().make_fpr_r_memory( fpPs0, gprRegister1, 0, PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory( fpPs0, gprRegister1, 0, PPCREC_FPR_LD_MODE_SINGLE, true);
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else
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else
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ppcImlGenContext->emitInst().make_fpr_r_memory_indexed( fpPs0, gprRegister1, gprRegister2, PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0, true);
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ppcImlGenContext->emitInst().make_fpr_r_memory_indexed( fpPs0, gprRegister1, gprRegister2, PPCREC_FPR_LD_MODE_SINGLE, true);
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if( ppcImlGenContext->LSQE )
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if( ppcImlGenContext->LSQE )
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{
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{
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DefinePS1(fpPs1, frD);
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DefinePS1(fpPs1, frD);
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@ -131,9 +131,9 @@ bool PPCRecompilerImlGen_STFS_STFSU_STFD_STFDU(ppcImlGenContext_t* ppcImlGenCont
|
||||||
imm = 0;
|
imm = 0;
|
||||||
}
|
}
|
||||||
if (isDouble)
|
if (isDouble)
|
||||||
ppcImlGenContext->emitInst().make_fpr_memory_r(fpPs0, gprRegister, imm, PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_memory_r(fpPs0, gprRegister, imm, PPCREC_FPR_ST_MODE_DOUBLE, true);
|
||||||
else
|
else
|
||||||
ppcImlGenContext->emitInst().make_fpr_memory_r(fpPs0, gprRegister, imm, PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_memory_r(fpPs0, gprRegister, imm, PPCREC_FPR_ST_MODE_SINGLE, true);
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -154,7 +154,7 @@ bool PPCRecompilerImlGen_STFSX_STFSUX_STFDX_STFDUX(ppcImlGenContext_t* ppcImlGen
|
||||||
ppcImlGenContext->emitInst().make_r_r_r(PPCREC_IML_OP_ADD, gprRegister1, gprRegister1, gprRegister2);
|
ppcImlGenContext->emitInst().make_r_r_r(PPCREC_IML_OP_ADD, gprRegister1, gprRegister1, gprRegister2);
|
||||||
}
|
}
|
||||||
DefinePS0(fpPs0, frS);
|
DefinePS0(fpPs0, frS);
|
||||||
auto mode = isDouble ? PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0 : PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0;
|
auto mode = isDouble ? PPCREC_FPR_ST_MODE_DOUBLE : PPCREC_FPR_ST_MODE_SINGLE;
|
||||||
if( ppcImlGenContext->LSQE )
|
if( ppcImlGenContext->LSQE )
|
||||||
{
|
{
|
||||||
if (hasUpdate)
|
if (hasUpdate)
|
||||||
|
@ -800,10 +800,10 @@ void PPCRecompilerImlGen_EmitPSQLoadCase(ppcImlGenContext_t* ppcImlGenContext, E
|
||||||
{
|
{
|
||||||
if (loadType == Espresso::PSQ_LOAD_TYPE::TYPE_F32)
|
if (loadType == Espresso::PSQ_LOAD_TYPE::TYPE_F32)
|
||||||
{
|
{
|
||||||
ppcImlGenContext->emitInst().make_fpr_r_memory(fprDPS0, gprA, imm, PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_r_memory(fprDPS0, gprA, imm, PPCREC_FPR_LD_MODE_SINGLE, true);
|
||||||
if(readPS1)
|
if(readPS1)
|
||||||
{
|
{
|
||||||
ppcImlGenContext->emitInst().make_fpr_r_memory(fprDPS1, gprA, imm + 4, PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_r_memory(fprDPS1, gprA, imm + 4, PPCREC_FPR_LD_MODE_SINGLE, true);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (loadType == Espresso::PSQ_LOAD_TYPE::TYPE_U16 || loadType == Espresso::PSQ_LOAD_TYPE::TYPE_S16)
|
if (loadType == Espresso::PSQ_LOAD_TYPE::TYPE_U16 || loadType == Espresso::PSQ_LOAD_TYPE::TYPE_S16)
|
||||||
|
@ -900,10 +900,10 @@ void PPCRecompilerImlGen_EmitPSQStoreCase(ppcImlGenContext_t* ppcImlGenContext,
|
||||||
cemu_assert_debug(!storePS1 || fprDPS1.IsValid());
|
cemu_assert_debug(!storePS1 || fprDPS1.IsValid());
|
||||||
if (storeType == Espresso::PSQ_LOAD_TYPE::TYPE_F32)
|
if (storeType == Espresso::PSQ_LOAD_TYPE::TYPE_F32)
|
||||||
{
|
{
|
||||||
ppcImlGenContext->emitInst().make_fpr_memory_r(fprDPS0, gprA, imm, PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_memory_r(fprDPS0, gprA, imm, PPCREC_FPR_ST_MODE_SINGLE, true);
|
||||||
if(storePS1)
|
if(storePS1)
|
||||||
{
|
{
|
||||||
ppcImlGenContext->emitInst().make_fpr_memory_r(fprDPS1, gprA, imm + 4, PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, true);
|
ppcImlGenContext->emitInst().make_fpr_memory_r(fprDPS1, gprA, imm + 4, PPCREC_FPR_ST_MODE_SINGLE, true);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else if (storeType == Espresso::PSQ_LOAD_TYPE::TYPE_U16 || storeType == Espresso::PSQ_LOAD_TYPE::TYPE_S16)
|
else if (storeType == Espresso::PSQ_LOAD_TYPE::TYPE_U16 || storeType == Espresso::PSQ_LOAD_TYPE::TYPE_S16)
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue