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PPCRec: Move IML register allocator
This commit is contained in:
Exzap
parent
231b5c5dc3
commit
411a83799c
13 changed files with 145 additions and 136 deletions
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@ -0,0 +1,399 @@
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#include "../PPCRecompiler.h"
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#include "../PPCRecompilerIml.h"
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#include "../PPCRecompilerX64.h"
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#include "IMLRegisterAllocatorRanges.h"
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#include "util/helpers/MemoryPool.h"
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void PPCRecRARange_addLink_perVirtualGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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if ((*root) && (*root)->range->virtualRegister != subrange->range->virtualRegister)
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assert_dbg();
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#endif
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subrange->link_sameVirtualRegisterGPR.next = *root;
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if (*root)
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(*root)->link_sameVirtualRegisterGPR.prev = subrange;
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subrange->link_sameVirtualRegisterGPR.prev = nullptr;
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*root = subrange;
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}
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void PPCRecRARange_addLink_allSubrangesGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
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{
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subrange->link_segmentSubrangesGPR.next = *root;
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if (*root)
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(*root)->link_segmentSubrangesGPR.prev = subrange;
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subrange->link_segmentSubrangesGPR.prev = nullptr;
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*root = subrange;
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}
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void PPCRecRARange_removeLink_perVirtualGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
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{
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raLivenessSubrange_t* tempPrev = subrange->link_sameVirtualRegisterGPR.prev;
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if (subrange->link_sameVirtualRegisterGPR.prev)
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subrange->link_sameVirtualRegisterGPR.prev->link_sameVirtualRegisterGPR.next = subrange->link_sameVirtualRegisterGPR.next;
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else
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(*root) = subrange->link_sameVirtualRegisterGPR.next;
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if (subrange->link_sameVirtualRegisterGPR.next)
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subrange->link_sameVirtualRegisterGPR.next->link_sameVirtualRegisterGPR.prev = tempPrev;
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_sameVirtualRegisterGPR.prev = (raLivenessSubrange_t*)1;
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subrange->link_sameVirtualRegisterGPR.next = (raLivenessSubrange_t*)1;
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#endif
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}
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void PPCRecRARange_removeLink_allSubrangesGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
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{
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raLivenessSubrange_t* tempPrev = subrange->link_segmentSubrangesGPR.prev;
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if (subrange->link_segmentSubrangesGPR.prev)
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subrange->link_segmentSubrangesGPR.prev->link_segmentSubrangesGPR.next = subrange->link_segmentSubrangesGPR.next;
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else
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(*root) = subrange->link_segmentSubrangesGPR.next;
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if (subrange->link_segmentSubrangesGPR.next)
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subrange->link_segmentSubrangesGPR.next->link_segmentSubrangesGPR.prev = tempPrev;
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_segmentSubrangesGPR.prev = (raLivenessSubrange_t*)1;
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subrange->link_segmentSubrangesGPR.next = (raLivenessSubrange_t*)1;
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#endif
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}
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MemoryPoolPermanentObjects<raLivenessRange_t> memPool_livenessRange(4096);
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MemoryPoolPermanentObjects<raLivenessSubrange_t> memPool_livenessSubrange(4096);
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raLivenessRange_t* PPCRecRA_createRangeBase(ppcImlGenContext_t* ppcImlGenContext, uint32 virtualRegister, uint32 name)
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{
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raLivenessRange_t* livenessRange = memPool_livenessRange.acquireObj();
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livenessRange->list_subranges.resize(0);
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livenessRange->virtualRegister = virtualRegister;
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livenessRange->name = name;
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livenessRange->physicalRegister = -1;
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ppcImlGenContext->raInfo.list_ranges.push_back(livenessRange);
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return livenessRange;
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}
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raLivenessSubrange_t* PPCRecRA_createSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_t* range, IMLSegment* imlSegment, sint32 startIndex, sint32 endIndex)
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{
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raLivenessSubrange_t* livenessSubrange = memPool_livenessSubrange.acquireObj();
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livenessSubrange->list_locations.resize(0);
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livenessSubrange->range = range;
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livenessSubrange->imlSegment = imlSegment;
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PPCRecompilerIml_setSegmentPoint(&livenessSubrange->start, imlSegment, startIndex);
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PPCRecompilerIml_setSegmentPoint(&livenessSubrange->end, imlSegment, endIndex);
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// default values
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livenessSubrange->hasStore = false;
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livenessSubrange->hasStoreDelayed = false;
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livenessSubrange->lastIterationIndex = 0;
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livenessSubrange->subrangeBranchNotTaken = nullptr;
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livenessSubrange->subrangeBranchTaken = nullptr;
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livenessSubrange->_noLoad = false;
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// add to range
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range->list_subranges.push_back(livenessSubrange);
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// add to segment
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PPCRecRARange_addLink_perVirtualGPR(&(imlSegment->raInfo.linkedList_perVirtualGPR[range->virtualRegister]), livenessSubrange);
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PPCRecRARange_addLink_allSubrangesGPR(&imlSegment->raInfo.linkedList_allSubranges, livenessSubrange);
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return livenessSubrange;
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}
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void _unlinkSubrange(raLivenessSubrange_t* subrange)
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{
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IMLSegment* imlSegment = subrange->imlSegment;
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PPCRecRARange_removeLink_perVirtualGPR(&imlSegment->raInfo.linkedList_perVirtualGPR[subrange->range->virtualRegister], subrange);
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PPCRecRARange_removeLink_allSubrangesGPR(&imlSegment->raInfo.linkedList_allSubranges, subrange);
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}
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void PPCRecRA_deleteSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange)
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{
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_unlinkSubrange(subrange);
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subrange->range->list_subranges.erase(std::find(subrange->range->list_subranges.begin(), subrange->range->list_subranges.end(), subrange));
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subrange->list_locations.clear();
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PPCRecompilerIml_removeSegmentPoint(&subrange->start);
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PPCRecompilerIml_removeSegmentPoint(&subrange->end);
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memPool_livenessSubrange.releaseObj(subrange);
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}
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void _PPCRecRA_deleteSubrangeNoUnlinkFromRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange)
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{
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_unlinkSubrange(subrange);
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PPCRecompilerIml_removeSegmentPoint(&subrange->start);
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PPCRecompilerIml_removeSegmentPoint(&subrange->end);
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memPool_livenessSubrange.releaseObj(subrange);
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}
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void PPCRecRA_deleteRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_t* range)
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{
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for (auto& subrange : range->list_subranges)
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{
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_PPCRecRA_deleteSubrangeNoUnlinkFromRange(ppcImlGenContext, subrange);
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}
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ppcImlGenContext->raInfo.list_ranges.erase(std::find(ppcImlGenContext->raInfo.list_ranges.begin(), ppcImlGenContext->raInfo.list_ranges.end(), range));
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memPool_livenessRange.releaseObj(range);
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}
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void PPCRecRA_deleteRangeNoUnlink(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_t* range)
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{
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for (auto& subrange : range->list_subranges)
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{
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_PPCRecRA_deleteSubrangeNoUnlinkFromRange(ppcImlGenContext, subrange);
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}
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memPool_livenessRange.releaseObj(range);
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}
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void PPCRecRA_deleteAllRanges(ppcImlGenContext_t* ppcImlGenContext)
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{
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for(auto& range : ppcImlGenContext->raInfo.list_ranges)
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{
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PPCRecRA_deleteRangeNoUnlink(ppcImlGenContext, range);
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}
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ppcImlGenContext->raInfo.list_ranges.clear();
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}
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void PPCRecRA_mergeRanges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_t* range, raLivenessRange_t* absorbedRange)
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{
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cemu_assert_debug(range != absorbedRange);
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cemu_assert_debug(range->virtualRegister == absorbedRange->virtualRegister);
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// move all subranges from absorbedRange to range
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for (auto& subrange : absorbedRange->list_subranges)
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{
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range->list_subranges.push_back(subrange);
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subrange->range = range;
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}
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absorbedRange->list_subranges.clear();
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PPCRecRA_deleteRange(ppcImlGenContext, absorbedRange);
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}
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void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, raLivenessSubrange_t* absorbedSubrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_debugValidateSubrange(absorbedSubrange);
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if (subrange->imlSegment != absorbedSubrange->imlSegment)
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assert_dbg();
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if (subrange->end.index > absorbedSubrange->start.index)
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assert_dbg();
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if (subrange->subrangeBranchTaken || subrange->subrangeBranchNotTaken)
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assert_dbg();
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if (subrange == absorbedSubrange)
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assert_dbg();
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#endif
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subrange->subrangeBranchTaken = absorbedSubrange->subrangeBranchTaken;
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subrange->subrangeBranchNotTaken = absorbedSubrange->subrangeBranchNotTaken;
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// merge usage locations
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for (auto& location : absorbedSubrange->list_locations)
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{
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subrange->list_locations.push_back(location);
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}
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absorbedSubrange->list_locations.clear();
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subrange->end.index = absorbedSubrange->end.index;
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_deleteSubrange(ppcImlGenContext, absorbedSubrange);
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}
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// remove all inter-segment connections from the range and split it into local ranges (also removes empty ranges)
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void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_t* range)
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{
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if (range->list_subranges.size() == 1)
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assert_dbg();
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for (auto& subrange : range->list_subranges)
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{
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if (subrange->list_locations.empty())
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continue;
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raLivenessRange_t* newRange = PPCRecRA_createRangeBase(ppcImlGenContext, range->virtualRegister, range->name);
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raLivenessSubrange_t* newSubrange = PPCRecRA_createSubrange(ppcImlGenContext, newRange, subrange->imlSegment, subrange->list_locations.data()[0].index, subrange->list_locations.data()[subrange->list_locations.size() - 1].index + 1);
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// copy locations
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for (auto& location : subrange->list_locations)
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{
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newSubrange->list_locations.push_back(location);
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}
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}
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// remove original range
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PPCRecRA_deleteRange(ppcImlGenContext, range);
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}
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#ifdef CEMU_DEBUG_ASSERT
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void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange)
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{
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// validate subrange
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if (subrange->subrangeBranchTaken && subrange->subrangeBranchTaken->imlSegment != subrange->imlSegment->nextSegmentBranchTaken)
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assert_dbg();
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if (subrange->subrangeBranchNotTaken && subrange->subrangeBranchNotTaken->imlSegment != subrange->imlSegment->nextSegmentBranchNotTaken)
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assert_dbg();
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}
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#else
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void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange) {}
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#endif
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// split subrange at the given index
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// After the split there will be two ranges/subranges:
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// head -> subrange is shortned to end at splitIndex
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// tail -> a new subrange that reaches from splitIndex to the end of the original subrange
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// if head has a physical register assigned it will not carry over to tail
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// The return value is the tail subrange
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// If trimToHole is true, the end of the head subrange and the start of the tail subrange will be moved to fit the locations
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// Ranges that begin at RA_INTER_RANGE_START are allowed and can be split
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raLivenessSubrange_t* PPCRecRA_splitLocalSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, sint32 splitIndex, bool trimToHole)
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{
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// validation
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#ifdef CEMU_DEBUG_ASSERT
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if (subrange->end.index == RA_INTER_RANGE_END || subrange->end.index == RA_INTER_RANGE_START)
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assert_dbg();
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if (subrange->start.index >= splitIndex)
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assert_dbg();
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if (subrange->end.index <= splitIndex)
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assert_dbg();
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#endif
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// create tail
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raLivenessRange_t* tailRange = PPCRecRA_createRangeBase(ppcImlGenContext, subrange->range->virtualRegister, subrange->range->name);
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raLivenessSubrange_t* tailSubrange = PPCRecRA_createSubrange(ppcImlGenContext, tailRange, subrange->imlSegment, splitIndex, subrange->end.index);
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// copy locations
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for (auto& location : subrange->list_locations)
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{
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if (location.index >= splitIndex)
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tailSubrange->list_locations.push_back(location);
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}
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// remove tail locations from head
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for (sint32 i = 0; i < subrange->list_locations.size(); i++)
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{
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raLivenessLocation_t* location = subrange->list_locations.data() + i;
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if (location->index >= splitIndex)
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{
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subrange->list_locations.resize(i);
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break;
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}
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}
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// adjust start/end
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if (trimToHole)
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{
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if (subrange->list_locations.empty())
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{
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subrange->end.index = subrange->start.index+1;
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}
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else
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{
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subrange->end.index = subrange->list_locations.back().index + 1;
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}
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if (tailSubrange->list_locations.empty())
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{
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assert_dbg(); // should not happen? (In this case we can just avoid generating a tail at all)
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}
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else
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{
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tailSubrange->start.index = tailSubrange->list_locations.front().index;
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}
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}
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return tailSubrange;
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}
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void PPCRecRA_updateOrAddSubrangeLocation(raLivenessSubrange_t* subrange, sint32 index, bool isRead, bool isWrite)
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{
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if (subrange->list_locations.empty())
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{
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subrange->list_locations.emplace_back(index, isRead, isWrite);
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return;
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}
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raLivenessLocation_t* lastLocation = subrange->list_locations.data() + (subrange->list_locations.size() - 1);
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cemu_assert_debug(lastLocation->index <= index);
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if (lastLocation->index == index)
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{
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// update
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lastLocation->isRead = lastLocation->isRead || isRead;
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lastLocation->isWrite = lastLocation->isWrite || isWrite;
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return;
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}
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// add new
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subrange->list_locations.emplace_back(index, isRead, isWrite);
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}
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sint32 PPCRecRARange_getReadWriteCost(IMLSegment* imlSegment)
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{
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sint32 v = imlSegment->loopDepth + 1;
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v *= 5;
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return v*v; // 25, 100, 225, 400
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}
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// calculate cost of entire range
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// ignores data flow and does not detect avoidable reads/stores
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sint32 PPCRecRARange_estimateCost(raLivenessRange_t* range)
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{
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sint32 cost = 0;
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// todo - this algorithm isn't accurate. If we have 10 parallel branches with a load each then the actual cost is still only that of one branch (plus minimal extra cost for generating more code).
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// currently we calculate the cost based on the most expensive entry/exit point
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sint32 mostExpensiveRead = 0;
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sint32 mostExpensiveWrite = 0;
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sint32 readCount = 0;
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sint32 writeCount = 0;
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for (auto& subrange : range->list_subranges)
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{
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if (subrange->start.index != RA_INTER_RANGE_START)
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{
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//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
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mostExpensiveRead = std::max(mostExpensiveRead, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
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readCount++;
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}
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if (subrange->end.index != RA_INTER_RANGE_END)
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{
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//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
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mostExpensiveWrite = std::max(mostExpensiveWrite, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
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writeCount++;
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}
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}
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cost = mostExpensiveRead + mostExpensiveWrite;
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cost = cost + (readCount + writeCount) / 10;
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return cost;
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}
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// calculate cost of range that it would have after calling PPCRecRA_explodeRange() on it
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sint32 PPCRecRARange_estimateAdditionalCostAfterRangeExplode(raLivenessRange_t* range)
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{
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sint32 cost = -PPCRecRARange_estimateCost(range);
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for (auto& subrange : range->list_subranges)
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{
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if (subrange->list_locations.empty())
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continue;
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cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment) * 2; // we assume a read and a store
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}
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return cost;
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}
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sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessSubrange_t* subrange, sint32 splitIndex)
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{
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// validation
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#ifdef CEMU_DEBUG_ASSERT
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if (subrange->end.index == RA_INTER_RANGE_END)
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assert_dbg();
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#endif
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sint32 cost = 0;
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// find split position in location list
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if (subrange->list_locations.empty())
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{
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assert_dbg(); // should not happen?
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return 0;
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}
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if (splitIndex <= subrange->list_locations.front().index)
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return 0;
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if (splitIndex > subrange->list_locations.back().index)
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return 0;
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// todo - determine exact cost of split subranges
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cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment) * 2; // currently we assume that the additional region will require a read and a store
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//for (sint32 f = 0; f < subrange->list_locations.size(); f++)
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//{
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// raLivenessLocation_t* location = subrange->list_locations.data() + f;
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// if (location->index >= splitIndex)
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// {
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// ...
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// return cost;
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// }
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//}
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return cost;
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}
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