mirror of
https://github.com/cemu-project/Cemu.git
synced 2025-07-09 00:11:17 +12:00
Remove PUBLIC_RELEASE flag and tie asserts to debug config (#287)
Removes the -DPUBLIC_RELEASE flag. Cemu's debug asserts are now only enabled if the build configuration is Debug. Similarly, on Windows the console is only shown for Debug builds.
This commit is contained in:
parent
b720d17a97
commit
3bceb39966
68 changed files with 154 additions and 186 deletions
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@ -153,7 +153,7 @@ private:
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void checkForCollisions()
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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uint32 endOfPrevious = 0;
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for (auto itr : map_ranges)
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{
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@ -78,7 +78,7 @@ void PPCRecompiler_enter(PPCInterpreter_t* hCPU, PPCREC_JUMP_ENTRY funcPtr)
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PPCRecompiler_enterRecompilerCode((uint64)funcPtr, (uint64)hCPU);
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_controlfp(prevState, _MCW_RC);
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// debug recompiler exit - useful to find frequently executed functions which couldn't be recompiled
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (hCPU->remainingCycles > 0 && GetAsyncKeyState(VK_F4))
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{
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auto t = std::chrono::high_resolution_clock::now();
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@ -415,7 +415,7 @@ uint32 PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext_t* ppcImlGe
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void PPCRecompilerImlGen_TW(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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{
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//#ifndef PUBLIC_RELEASE
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//#ifdef CEMU_DEBUG_ASSERT
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// PPCRecompilerImlGen_generateNewInstruction_macro(ppcImlGenContext, PPCREC_IML_MACRO_DEBUGBREAK, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, 0);
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//#endif
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PPCRecompilerImlGen_generateNewInstruction_macro(ppcImlGenContext, PPCREC_IML_MACRO_LEAVE, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, 0);
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@ -2271,7 +2271,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
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// if nb == 4 this instruction immitates LWZ
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if( rA == 0 )
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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return false;
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@ -2291,7 +2291,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
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// if nb == 2 this instruction immitates a LHZ but the result is shifted left by 16 bits
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if( rA == 0 )
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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return false;
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@ -2313,7 +2313,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
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// if nb == 3 this instruction loads a 3-byte big-endian and the result is shifted left by 8 bits
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if( rA == 0 )
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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return false;
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@ -4560,7 +4560,7 @@ bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext
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if( ppcImlGenContext.imlList[i].type == PPCREC_IML_TYPE_JUMPMARK )
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{
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ppcImlGenContext.imlList[i].op_jumpmark.flags |= PPCREC_IML_OP_FLAG_UNUSED;
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (map_jumpMarks.find(ppcImlGenContext.imlList[i].op_jumpmark.address) != map_jumpMarks.end())
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assert_dbg();
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#endif
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@ -2151,7 +2151,7 @@ void _reorderConditionModifyInstructions(PPCRecImlSegment_t* imlSegment)
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}
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// move CR setter instruction
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if ((unsafeInstructionIndex + 1) <= crSetterInstructionIndex)
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assert_dbg();
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#endif
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@ -6,7 +6,7 @@
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void PPCRecRARange_addLink_perVirtualGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if ((*root) && (*root)->range->virtualRegister != subrange->range->virtualRegister)
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assert_dbg();
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#endif
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@ -35,7 +35,7 @@ void PPCRecRARange_removeLink_perVirtualGPR(raLivenessSubrange_t** root, raLiven
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(*root) = subrange->link_sameVirtualRegisterGPR.next;
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if (subrange->link_sameVirtualRegisterGPR.next)
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subrange->link_sameVirtualRegisterGPR.next->link_sameVirtualRegisterGPR.prev = tempPrev;
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_sameVirtualRegisterGPR.prev = (raLivenessSubrange_t*)1;
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subrange->link_sameVirtualRegisterGPR.next = (raLivenessSubrange_t*)1;
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#endif
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@ -50,7 +50,7 @@ void PPCRecRARange_removeLink_allSubrangesGPR(raLivenessSubrange_t** root, raLiv
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(*root) = subrange->link_segmentSubrangesGPR.next;
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if (subrange->link_segmentSubrangesGPR.next)
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subrange->link_segmentSubrangesGPR.next->link_segmentSubrangesGPR.prev = tempPrev;
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_segmentSubrangesGPR.prev = (raLivenessSubrange_t*)1;
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subrange->link_segmentSubrangesGPR.next = (raLivenessSubrange_t*)1;
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#endif
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@ -162,7 +162,7 @@ void PPCRecRA_mergeRanges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_
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void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, raLivenessSubrange_t* absorbedSubrange)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_debugValidateSubrange(absorbedSubrange);
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if (subrange->imlSegment != absorbedSubrange->imlSegment)
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@ -212,7 +212,7 @@ void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange
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PPCRecRA_deleteRange(ppcImlGenContext, range);
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}
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange)
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{
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// validate subrange
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@ -236,7 +236,7 @@ void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange) {}
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raLivenessSubrange_t* PPCRecRA_splitLocalSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, sint32 splitIndex, bool trimToHole)
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{
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// validation
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (subrange->end.index == RA_INTER_RANGE_END || subrange->end.index == RA_INTER_RANGE_START)
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assert_dbg();
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if (subrange->start.index >= splitIndex)
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@ -364,7 +364,7 @@ sint32 PPCRecRARange_estimateAdditionalCostAfterRangeExplode(raLivenessRange_t*
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sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessSubrange_t* subrange, sint32 splitIndex)
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{
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// validation
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (subrange->end.index == RA_INTER_RANGE_END)
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assert_dbg();
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#endif
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@ -91,7 +91,7 @@ raRegisterState_t* PPCRecRA_getRegisterState(raRegisterState_t* regState, sint32
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{
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if (regState[i].virtualRegister == virtualRegister)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (regState[i].physicalRegister < 0)
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assert_dbg();
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#endif
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@ -300,7 +300,7 @@ void _sortSegmentAllSubrangesLinkedList(PPCRecImlSegment_t* imlSegment)
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subrangeList[i]->link_segmentSubrangesGPR.next = subrangeList[i + 1];
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}
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// validate list
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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sint32 count2 = 0;
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subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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sint32 currentStartIndex = RA_INTER_RANGE_START;
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@ -342,7 +342,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, PPCRe
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raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
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if (liverange->end.index <= currentIndex && liverange->end.index != RA_INTER_RANGE_END)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (liverange->subrangeBranchTaken || liverange->subrangeBranchNotTaken)
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assert_dbg(); // infinite subranges should not expire
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#endif
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@ -356,7 +356,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, PPCRe
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if (subrangeItr->range->physicalRegister >= 0)
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{
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// verify if register is actually available
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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{
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raLivenessSubrange_t* liverangeItr = liveInfo.liveRangeList[f];
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@ -778,7 +778,7 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
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{
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liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
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liveInfo.liveRangesCount++;
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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// load GPR
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if (subrangeItr->_noLoad == false)
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{
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@ -105,7 +105,7 @@ void PPCRecRA_createSegmentLivenessRanges(ppcImlGenContext_t* ppcImlGenContext,
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for (sint32 i = 0; i < PPC_REC_MAX_VIRTUAL_GPR; i++)
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{
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vGPR2Subrange[i] = imlSegment->raInfo.linkedList_perVirtualGPR[i];
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (vGPR2Subrange[i] && vGPR2Subrange[i]->link_sameVirtualRegisterGPR.next != nullptr)
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assert_dbg();
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#endif
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@ -129,7 +129,7 @@ void PPCRecRA_createSegmentLivenessRanges(ppcImlGenContext_t* ppcImlGenContext,
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bool isWrite = (t == 3);
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// add location
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PPCRecRA_updateOrAddSubrangeLocation(vGPR2Subrange[virtualRegister], index, isWrite == false, isWrite);
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (index < vGPR2Subrange[virtualRegister]->start.index)
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assert_dbg();
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if (index+1 > vGPR2Subrange[virtualRegister]->end.index)
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void _PPCRecRA_connectRanges(ppcImlGenContext_t* ppcImlGenContext, sint32 vGPR, PPCRecImlSegment_t** route, sint32 routeDepth)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (routeDepth < 2)
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assert_dbg();
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#endif
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@ -226,7 +226,7 @@ void _PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, PPCR
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void PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlSegment_t* currentSegment, sint32 vGPR)
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{
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (currentSegment->raDistances.reg[vGPR].usageEnd < 0)
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assert_dbg();
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#endif
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else
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instructionsUntilEndOfSeg = currentSegment->imlListCount - currentSegment->raDistances.reg[vGPR].usageEnd;
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (instructionsUntilEndOfSeg < 0)
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assert_dbg();
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#endif
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@ -269,7 +269,7 @@ void PPCRecRA_mergeCloseRangesForSegmentV2(ppcImlGenContext_t* ppcImlGenContext,
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// check and extend if possible
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PPCRecRA_checkAndTryExtendRange(ppcImlGenContext, imlSegment, i);
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}
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#ifndef PUBLIC_RELEASE
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#ifdef CEMU_DEBUG_ASSERT
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if (imlSegment->list_prevSegments.empty() == false && imlSegment->isEnterable)
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assert_dbg();
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if ((imlSegment->nextSegmentBranchNotTaken != nullptr || imlSegment->nextSegmentBranchTaken != nullptr) && imlSegment->nextSegmentIsUncertain)
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