Remove PUBLIC_RELEASE flag and tie asserts to debug config (#287)

Removes the -DPUBLIC_RELEASE flag. Cemu's debug asserts are now only enabled if the build configuration is Debug. Similarly, on Windows the console is only shown for Debug builds.
This commit is contained in:
Exzap 2022-09-24 08:43:27 +02:00 committed by GitHub
parent b720d17a97
commit 3bceb39966
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
68 changed files with 154 additions and 186 deletions

View file

@ -153,7 +153,7 @@ private:
void checkForCollisions()
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
uint32 endOfPrevious = 0;
for (auto itr : map_ranges)
{

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@ -78,7 +78,7 @@ void PPCRecompiler_enter(PPCInterpreter_t* hCPU, PPCREC_JUMP_ENTRY funcPtr)
PPCRecompiler_enterRecompilerCode((uint64)funcPtr, (uint64)hCPU);
_controlfp(prevState, _MCW_RC);
// debug recompiler exit - useful to find frequently executed functions which couldn't be recompiled
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (hCPU->remainingCycles > 0 && GetAsyncKeyState(VK_F4))
{
auto t = std::chrono::high_resolution_clock::now();

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@ -415,7 +415,7 @@ uint32 PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext_t* ppcImlGe
void PPCRecompilerImlGen_TW(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
{
//#ifndef PUBLIC_RELEASE
//#ifdef CEMU_DEBUG_ASSERT
// PPCRecompilerImlGen_generateNewInstruction_macro(ppcImlGenContext, PPCREC_IML_MACRO_DEBUGBREAK, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, 0);
//#endif
PPCRecompilerImlGen_generateNewInstruction_macro(ppcImlGenContext, PPCREC_IML_MACRO_LEAVE, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, 0);
@ -2271,7 +2271,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
// if nb == 4 this instruction immitates LWZ
if( rA == 0 )
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
assert_dbg(); // special form where gpr is ignored and only imm is used
#endif
return false;
@ -2291,7 +2291,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
// if nb == 2 this instruction immitates a LHZ but the result is shifted left by 16 bits
if( rA == 0 )
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
assert_dbg(); // special form where gpr is ignored and only imm is used
#endif
return false;
@ -2313,7 +2313,7 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
// if nb == 3 this instruction loads a 3-byte big-endian and the result is shifted left by 8 bits
if( rA == 0 )
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
assert_dbg(); // special form where gpr is ignored and only imm is used
#endif
return false;
@ -4560,7 +4560,7 @@ bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext
if( ppcImlGenContext.imlList[i].type == PPCREC_IML_TYPE_JUMPMARK )
{
ppcImlGenContext.imlList[i].op_jumpmark.flags |= PPCREC_IML_OP_FLAG_UNUSED;
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (map_jumpMarks.find(ppcImlGenContext.imlList[i].op_jumpmark.address) != map_jumpMarks.end())
assert_dbg();
#endif

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@ -2151,7 +2151,7 @@ void _reorderConditionModifyInstructions(PPCRecImlSegment_t* imlSegment)
}
// move CR setter instruction
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if ((unsafeInstructionIndex + 1) <= crSetterInstructionIndex)
assert_dbg();
#endif

View file

@ -6,7 +6,7 @@
void PPCRecRARange_addLink_perVirtualGPR(raLivenessSubrange_t** root, raLivenessSubrange_t* subrange)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if ((*root) && (*root)->range->virtualRegister != subrange->range->virtualRegister)
assert_dbg();
#endif
@ -35,7 +35,7 @@ void PPCRecRARange_removeLink_perVirtualGPR(raLivenessSubrange_t** root, raLiven
(*root) = subrange->link_sameVirtualRegisterGPR.next;
if (subrange->link_sameVirtualRegisterGPR.next)
subrange->link_sameVirtualRegisterGPR.next->link_sameVirtualRegisterGPR.prev = tempPrev;
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
subrange->link_sameVirtualRegisterGPR.prev = (raLivenessSubrange_t*)1;
subrange->link_sameVirtualRegisterGPR.next = (raLivenessSubrange_t*)1;
#endif
@ -50,7 +50,7 @@ void PPCRecRARange_removeLink_allSubrangesGPR(raLivenessSubrange_t** root, raLiv
(*root) = subrange->link_segmentSubrangesGPR.next;
if (subrange->link_segmentSubrangesGPR.next)
subrange->link_segmentSubrangesGPR.next->link_segmentSubrangesGPR.prev = tempPrev;
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
subrange->link_segmentSubrangesGPR.prev = (raLivenessSubrange_t*)1;
subrange->link_segmentSubrangesGPR.next = (raLivenessSubrange_t*)1;
#endif
@ -162,7 +162,7 @@ void PPCRecRA_mergeRanges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange_
void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, raLivenessSubrange_t* absorbedSubrange)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
PPCRecRA_debugValidateSubrange(subrange);
PPCRecRA_debugValidateSubrange(absorbedSubrange);
if (subrange->imlSegment != absorbedSubrange->imlSegment)
@ -212,7 +212,7 @@ void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange
PPCRecRA_deleteRange(ppcImlGenContext, range);
}
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange)
{
// validate subrange
@ -236,7 +236,7 @@ void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange) {}
raLivenessSubrange_t* PPCRecRA_splitLocalSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessSubrange_t* subrange, sint32 splitIndex, bool trimToHole)
{
// validation
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (subrange->end.index == RA_INTER_RANGE_END || subrange->end.index == RA_INTER_RANGE_START)
assert_dbg();
if (subrange->start.index >= splitIndex)
@ -364,7 +364,7 @@ sint32 PPCRecRARange_estimateAdditionalCostAfterRangeExplode(raLivenessRange_t*
sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessSubrange_t* subrange, sint32 splitIndex)
{
// validation
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (subrange->end.index == RA_INTER_RANGE_END)
assert_dbg();
#endif

View file

@ -91,7 +91,7 @@ raRegisterState_t* PPCRecRA_getRegisterState(raRegisterState_t* regState, sint32
{
if (regState[i].virtualRegister == virtualRegister)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (regState[i].physicalRegister < 0)
assert_dbg();
#endif
@ -300,7 +300,7 @@ void _sortSegmentAllSubrangesLinkedList(PPCRecImlSegment_t* imlSegment)
subrangeList[i]->link_segmentSubrangesGPR.next = subrangeList[i + 1];
}
// validate list
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
sint32 count2 = 0;
subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
sint32 currentStartIndex = RA_INTER_RANGE_START;
@ -342,7 +342,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, PPCRe
raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
if (liverange->end.index <= currentIndex && liverange->end.index != RA_INTER_RANGE_END)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (liverange->subrangeBranchTaken || liverange->subrangeBranchNotTaken)
assert_dbg(); // infinite subranges should not expire
#endif
@ -356,7 +356,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, PPCRe
if (subrangeItr->range->physicalRegister >= 0)
{
// verify if register is actually available
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
{
raLivenessSubrange_t* liverangeItr = liveInfo.liveRangeList[f];
@ -778,7 +778,7 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
{
liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
liveInfo.liveRangesCount++;
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
// load GPR
if (subrangeItr->_noLoad == false)
{

View file

@ -105,7 +105,7 @@ void PPCRecRA_createSegmentLivenessRanges(ppcImlGenContext_t* ppcImlGenContext,
for (sint32 i = 0; i < PPC_REC_MAX_VIRTUAL_GPR; i++)
{
vGPR2Subrange[i] = imlSegment->raInfo.linkedList_perVirtualGPR[i];
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (vGPR2Subrange[i] && vGPR2Subrange[i]->link_sameVirtualRegisterGPR.next != nullptr)
assert_dbg();
#endif
@ -129,7 +129,7 @@ void PPCRecRA_createSegmentLivenessRanges(ppcImlGenContext_t* ppcImlGenContext,
bool isWrite = (t == 3);
// add location
PPCRecRA_updateOrAddSubrangeLocation(vGPR2Subrange[virtualRegister], index, isWrite == false, isWrite);
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (index < vGPR2Subrange[virtualRegister]->start.index)
assert_dbg();
if (index+1 > vGPR2Subrange[virtualRegister]->end.index)
@ -172,7 +172,7 @@ void PPCRecRA_extendRangeToBeginningOfSegment(ppcImlGenContext_t* ppcImlGenConte
void _PPCRecRA_connectRanges(ppcImlGenContext_t* ppcImlGenContext, sint32 vGPR, PPCRecImlSegment_t** route, sint32 routeDepth)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (routeDepth < 2)
assert_dbg();
#endif
@ -226,7 +226,7 @@ void _PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, PPCR
void PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlSegment_t* currentSegment, sint32 vGPR)
{
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (currentSegment->raDistances.reg[vGPR].usageEnd < 0)
assert_dbg();
#endif
@ -239,7 +239,7 @@ void PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, PPCRe
else
instructionsUntilEndOfSeg = currentSegment->imlListCount - currentSegment->raDistances.reg[vGPR].usageEnd;
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (instructionsUntilEndOfSeg < 0)
assert_dbg();
#endif
@ -269,7 +269,7 @@ void PPCRecRA_mergeCloseRangesForSegmentV2(ppcImlGenContext_t* ppcImlGenContext,
// check and extend if possible
PPCRecRA_checkAndTryExtendRange(ppcImlGenContext, imlSegment, i);
}
#ifndef PUBLIC_RELEASE
#ifdef CEMU_DEBUG_ASSERT
if (imlSegment->list_prevSegments.empty() == false && imlSegment->isEnterable)
assert_dbg();
if ((imlSegment->nextSegmentBranchNotTaken != nullptr || imlSegment->nextSegmentBranchTaken != nullptr) && imlSegment->nextSegmentIsUncertain)