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GX2+TCL: Reimplement command buffer submission
- GX2 utilizes TCL(.rpl) API for command submission instead of directly writing to an internal GPU fifo - Submission & retire timestamps are correctly implemented as incremental counters - Command buffering behaviour matches console - Fixes race conditions on aarch64
This commit is contained in:
Exzap
parent
96765e4ac6
commit
28ea70b6d8
21 changed files with 761 additions and 472 deletions
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@ -4,178 +4,397 @@
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#include "Cafe/HW/Latte/Core/LattePM4.h"
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#include "Cafe/OS/libs/coreinit/coreinit.h"
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#include "Cafe/OS/libs/coreinit/coreinit_Thread.h"
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#include "Cafe/OS/libs/TCL/TCL.h"
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#include "Cafe/HW/Latte/ISA/RegDefines.h"
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#include "GX2.h"
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#include "GX2_Command.h"
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#include "GX2_Shader.h"
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#include "GX2_Misc.h"
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#include "OS/libs/coreinit/coreinit_MEM.h"
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extern uint8* gxRingBufferReadPtr;
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GX2WriteGatherPipeState gx2WriteGatherPipe = { 0 };
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namespace GX2
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{
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GX2PerCoreCBState s_perCoreCBState[Espresso::CORE_COUNT];
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}
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void gx2WriteGather_submitU32AsBE(uint32 v)
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{
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uint32 coreIndex = PPCInterpreter_getCoreIndex(PPCInterpreter_getCurrentInstance());
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if (gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] == NULL)
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if (GX2::s_perCoreCBState[coreIndex].currentWritePtr == nullptr)
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return;
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*(uint32*)(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]) = _swapEndianU32(v);
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(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]) += 4;
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*(uint32*)(GX2::s_perCoreCBState[coreIndex].currentWritePtr) = _swapEndianU32(v);
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GX2::s_perCoreCBState[coreIndex].currentWritePtr++;
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cemu_assert_debug(GX2::s_perCoreCBState[coreIndex].currentWritePtr <= (GX2::s_perCoreCBState[coreIndex].bufferPtr + GX2::s_perCoreCBState[coreIndex].bufferSizeInU32s));
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}
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void gx2WriteGather_submitU32AsLE(uint32 v)
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{
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uint32 coreIndex = PPCInterpreter_getCoreIndex(PPCInterpreter_getCurrentInstance());
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if (gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] == NULL)
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if (GX2::s_perCoreCBState[coreIndex].currentWritePtr == nullptr)
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return;
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*(uint32*)(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]) = v;
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(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]) += 4;
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*(uint32*)(GX2::s_perCoreCBState[coreIndex].currentWritePtr) = v;
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GX2::s_perCoreCBState[coreIndex].currentWritePtr++;
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cemu_assert_debug(GX2::s_perCoreCBState[coreIndex].currentWritePtr <= (GX2::s_perCoreCBState[coreIndex].bufferPtr + GX2::s_perCoreCBState[coreIndex].bufferSizeInU32s));
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}
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void gx2WriteGather_submitU32AsLEArray(uint32* v, uint32 numValues)
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{
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uint32 coreIndex = PPCInterpreter_getCoreIndex(PPCInterpreter_getCurrentInstance());
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if (gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] == NULL)
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if (GX2::s_perCoreCBState[coreIndex].currentWritePtr == nullptr)
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return;
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memcpy_dwords((*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]), v, numValues);
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(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex]) += 4 * numValues;
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memcpy_dwords(GX2::s_perCoreCBState[coreIndex].currentWritePtr, v, numValues);
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GX2::s_perCoreCBState[coreIndex].currentWritePtr += numValues;
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cemu_assert_debug(GX2::s_perCoreCBState[coreIndex].currentWritePtr <= (GX2::s_perCoreCBState[coreIndex].bufferPtr + GX2::s_perCoreCBState[coreIndex].bufferSizeInU32s));
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}
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namespace GX2
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{
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sint32 gx2WriteGatherCurrentMainCoreIndex = -1;
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bool gx2WriteGatherInited = false;
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void GX2WriteGather_ResetToDefaultState()
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struct GX2CommandState // mapped to PPC space since the GPU writes here
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{
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gx2WriteGatherCurrentMainCoreIndex = -1;
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gx2WriteGatherInited = false;
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}
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// command pool
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MEMPTR<uint32be> commandPoolBase;
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uint32 commandPoolSizeInU32s;
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MEMPTR<uint32be> gpuCommandReadPtr;
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// timestamp
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uint64be lastSubmissionTime;
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};
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void GX2Init_writeGather() // init write gather, make current core
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SysAllocator<GX2CommandState> s_commandState;
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GX2PerCoreCBState s_mainCoreLastCommandState;
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bool s_cbBufferIsInternallyAllocated;
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void GX2Command_StartNewCommandBuffer(uint32 numU32s);
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// called from GX2Init. Allocates a 4MB memory chunk from which command buffers are suballocated from
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void GX2Init_commandBufferPool(void* bufferBase, uint32 bufferSize)
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{
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if (gx2WriteGatherPipe.gxRingBuffer == NULL)
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gx2WriteGatherPipe.gxRingBuffer = (uint8*)malloc(GX2_COMMAND_RING_BUFFER_SIZE);
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if (gx2WriteGatherCurrentMainCoreIndex == sGX2MainCoreIndex)
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return; // write gather already configured for same core
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for (sint32 i = 0; i < PPC_CORE_COUNT; i++)
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cemu_assert_debug(!s_commandState->commandPoolBase); // should not be allocated already
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// setup command buffer pool. If not provided allocate a 4MB or custom size buffer
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uint32 poolSize = bufferSize ? bufferSize : 0x400000; // 4MB (can be overwritten by custom GX2Init parameters?)
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if (bufferBase)
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{
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if (i == sGX2MainCoreIndex)
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s_commandState->commandPoolBase = (uint32be*)bufferBase;
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s_cbBufferIsInternallyAllocated = false;
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}
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else
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{
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s_commandState->commandPoolBase = (uint32be*)coreinit::_weak_MEMAllocFromDefaultHeapEx(poolSize, 0x100);
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s_cbBufferIsInternallyAllocated = true;
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}
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if (!s_commandState->commandPoolBase)
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{
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cemuLog_log(LogType::Force, "GX2: Failed to allocate command buffer pool");
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}
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s_commandState->commandPoolSizeInU32s = poolSize / sizeof(uint32be);
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s_commandState->gpuCommandReadPtr = s_commandState->commandPoolBase;
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// init per-core command buffer state
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for (uint32 i = 0; i < Espresso::CORE_COUNT; i++)
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{
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s_perCoreCBState[i].bufferPtr = nullptr;
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s_perCoreCBState[i].bufferSizeInU32s = 0;
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s_perCoreCBState[i].currentWritePtr = nullptr;
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}
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// start first command buffer for main core
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GX2Command_StartNewCommandBuffer(0x100);
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}
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void GX2Shutdown_commandBufferPool()
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{
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if (!s_commandState->commandPoolBase)
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return;
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if (s_cbBufferIsInternallyAllocated)
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coreinit::_weak_MEMFreeToDefaultHeap(s_commandState->commandPoolBase.GetPtr());
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s_cbBufferIsInternallyAllocated = false;
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s_commandState->commandPoolBase = nullptr;
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s_commandState->commandPoolSizeInU32s = 0;
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s_commandState->gpuCommandReadPtr = nullptr;
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}
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// current position of where the GPU is reading from. Updated via a memory write command submitted to the GPU
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uint32 GX2Command_GetPoolGPUReadIndex()
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{
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stdx::atomic_ref<MEMPTR<uint32be>> _readPtr(s_commandState->gpuCommandReadPtr);
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MEMPTR<uint32be> currentReadPtr = _readPtr.load();
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cemu_assert_debug(currentReadPtr);
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return (uint32)(currentReadPtr.GetPtr() - s_commandState->commandPoolBase.GetPtr());
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}
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void GX2Command_WaitForNextBufferRetired()
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{
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uint64 retiredTimeStamp = GX2GetRetiredTimeStamp();
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retiredTimeStamp += 1;
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// but cant be higher than the submission timestamp
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stdx::atomic_ref<uint64be> _lastSubmissionTime(s_commandState->lastSubmissionTime);
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uint64 submissionTimeStamp = _lastSubmissionTime.load();
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if (retiredTimeStamp > submissionTimeStamp)
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retiredTimeStamp = submissionTimeStamp;
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GX2WaitTimeStamp(retiredTimeStamp);
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}
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void GX2Command_SetupCoreCommandBuffer(uint32be* buffer, uint32 sizeInU32s, bool isDisplayList)
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{
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uint32 coreIndex = coreinit::OSGetCoreId();
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auto& coreCBState = s_perCoreCBState[coreIndex];
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coreCBState.bufferPtr = buffer;
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coreCBState.bufferSizeInU32s = sizeInU32s;
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coreCBState.currentWritePtr = buffer;
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coreCBState.isDisplayList = isDisplayList;
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}
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void GX2Command_StartNewCommandBuffer(uint32 numU32s)
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{
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uint32 coreIndex = coreinit::OSGetCoreId();
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auto& coreCBState = s_perCoreCBState[coreIndex];
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numU32s = std::max<uint32>(numU32s, 0x100);
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// grab space from command buffer pool and if necessary wait for it
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uint32be* bufferPtr = nullptr;
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uint32 bufferSizeInU32s = 0;
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uint32 readIndex;
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while (true)
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{
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// try to grab buffer data from first available spot:
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// 1. At the current write location up to the end of the buffer (avoiding an overlap with the read location)
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// 2. From the start of the buffer up to the read location
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readIndex = GX2Command_GetPoolGPUReadIndex();
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uint32be* nextWritePos = coreCBState.bufferPtr ? coreCBState.bufferPtr + coreCBState.bufferSizeInU32s : s_commandState->commandPoolBase.GetPtr();
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uint32 writeIndex = nextWritePos - s_commandState->commandPoolBase;
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uint32 poolSizeInU32s = s_commandState->commandPoolSizeInU32s;
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// readIndex == writeIndex can mean either buffer full or buffer empty
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// we could use GX2GetRetiredTimeStamp() == GX2GetLastSubmittedTimeStamp() to determine if the buffer is truly empty
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// but this can have false negatives since the last submission timestamp is updated independently of the read index
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// so instead we just avoid ever filling the buffer completely
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cemu_assert_debug(readIndex < poolSizeInU32s);
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cemu_assert_debug(writeIndex < poolSizeInU32s);
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if (writeIndex < readIndex)
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{
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gx2WriteGatherPipe.writeGatherPtrGxBuffer[i] = gx2WriteGatherPipe.gxRingBuffer;
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gx2WriteGatherPipe.writeGatherPtrWrite[i] = &gx2WriteGatherPipe.writeGatherPtrGxBuffer[i];
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// writeIndex has wrapped around
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uint32 wordsAvailable = readIndex - writeIndex;
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if (wordsAvailable > 0)
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wordsAvailable--; // avoid writeIndex becoming equal to readIndex
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if (wordsAvailable >= numU32s)
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{
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bufferPtr = s_commandState->commandPoolBase + writeIndex;
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bufferSizeInU32s = wordsAvailable;
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break;
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}
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}
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else
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{
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gx2WriteGatherPipe.writeGatherPtrGxBuffer[i] = NULL;
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gx2WriteGatherPipe.writeGatherPtrWrite[i] = NULL;
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uint32 wordsAvailable = poolSizeInU32s - writeIndex;
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if (wordsAvailable > 0)
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wordsAvailable--; // avoid writeIndex becoming equal to readIndex
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if (wordsAvailable >= numU32s)
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{
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bufferPtr = nextWritePos;
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bufferSizeInU32s = wordsAvailable;
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break;
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}
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// not enough space at end of buffer, try to grab from the beginning of the buffer
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wordsAvailable = readIndex;
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if (wordsAvailable > 0)
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wordsAvailable--; // avoid writeIndex becoming equal to readIndex
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if (wordsAvailable >= numU32s)
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{
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bufferPtr = s_commandState->commandPoolBase;
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bufferSizeInU32s = wordsAvailable;
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break;
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}
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}
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gx2WriteGatherPipe.displayListStart[i] = MPTR_NULL;
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gx2WriteGatherPipe.writeGatherPtrDisplayList[i] = NULL;
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gx2WriteGatherPipe.displayListMaxSize[i] = 0;
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GX2Command_WaitForNextBufferRetired();
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}
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cemu_assert_debug(bufferPtr);
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bufferSizeInU32s = std::min<uint32>(numU32s, 0x20000); // size cap
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#ifdef CEMU_DEBUG_ASSERT
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uint32 newWriteIndex = ((bufferPtr - s_commandState->commandPoolBase) + bufferSizeInU32s) % s_commandState->commandPoolSizeInU32s;
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cemu_assert_debug(newWriteIndex != readIndex);
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#endif
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// setup buffer and make it the current write gather target
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cemu_assert_debug(bufferPtr >= s_commandState->commandPoolBase && (bufferPtr + bufferSizeInU32s) <= s_commandState->commandPoolBase + s_commandState->commandPoolSizeInU32s);
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GX2Command_SetupCoreCommandBuffer(bufferPtr, bufferSizeInU32s, false);
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}
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void GX2Command_SubmitCommandBuffer(uint32be* buffer, uint32 sizeInU32s, MEMPTR<uint32be>* completionGPUReadPointer, bool triggerMarkerInterrupt)
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{
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uint32be cmd[10];
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uint32 cmdLen = 4;
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cmd[0] = pm4HeaderType3(IT_INDIRECT_BUFFER_PRIV, 3);
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cmd[1] = memory_virtualToPhysical(MEMPTR<void>(buffer).GetMPTR());
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cmd[2] = 0x00000000; // address high bits
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cmd[3] = sizeInU32s;
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if (completionGPUReadPointer)
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{
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// append command to update completionGPUReadPointer after the GPU is done with the command buffer
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cmd[4] = pm4HeaderType3(IT_MEM_WRITE, 4);
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cmd[5] = memory_virtualToPhysical(MEMPTR<void>(completionGPUReadPointer).GetMPTR()) | 2;
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cmd[6] = 0x40000;
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cmd[7] = MEMPTR<void>(buffer + sizeInU32s).GetMPTR(); // value to write
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cmd[8] = 0x00000000;
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cmdLen = 9;
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}
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betype<TCL::TCLSubmissionFlag> submissionFlags{};
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if (!triggerMarkerInterrupt)
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submissionFlags |= TCL::TCLSubmissionFlag::NO_MARKER_INTERRUPT;
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submissionFlags |= TCL::TCLSubmissionFlag::USE_RETIRED_MARKER;
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TCL::TCLSubmitToRing(cmd, cmdLen, &submissionFlags, &s_commandState->lastSubmissionTime);
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}
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void GX2Command_PadCurrentBuffer()
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{
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uint32 coreIndex = coreinit::OSGetCoreId();
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auto& coreCBState = s_perCoreCBState[coreIndex];
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if (!coreCBState.currentWritePtr)
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return;
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uint32 writeDistance = (uint32)(coreCBState.currentWritePtr - coreCBState.bufferPtr);
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if ((writeDistance&7) != 0)
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{
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uint32 distanceToPad = 0x8 - (writeDistance & 0x7);
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while (distanceToPad)
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{
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*coreCBState.currentWritePtr = pm4HeaderType2Filler();
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coreCBState.currentWritePtr++;
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distanceToPad--;
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}
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}
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}
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void GX2Command_Flush(uint32 numU32sForNextBuffer, bool triggerMarkerInterrupt)
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{
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uint32 coreIndex = coreinit::OSGetCoreId();
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auto& coreCBState = s_perCoreCBState[coreIndex];
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if (coreCBState.isDisplayList)
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{
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// display list
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cemu_assert_debug((uint32)(coreCBState.currentWritePtr - coreCBState.bufferPtr) < coreCBState.bufferSizeInU32s);
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cemuLog_logDebugOnce(LogType::Force, "GX2 flush called on display list");
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}
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else
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{
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// command buffer
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if (coreCBState.currentWritePtr != coreCBState.bufferPtr)
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{
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// pad the command buffer to 32 byte alignment
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GX2Command_PadCurrentBuffer();
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// submit it to the GPU
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uint32 bufferLength = (uint32)(coreCBState.currentWritePtr - coreCBState.bufferPtr);
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cemu_assert_debug(bufferLength <= coreCBState.bufferSizeInU32s);
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GX2Command_SubmitCommandBuffer(coreCBState.bufferPtr, bufferLength, &s_commandState->gpuCommandReadPtr, triggerMarkerInterrupt);
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GX2Command_StartNewCommandBuffer(numU32sForNextBuffer);
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}
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else
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{
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// current buffer is empty so we dont need to queue it
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if (numU32sForNextBuffer > s_commandState->commandPoolSizeInU32s)
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GX2Command_StartNewCommandBuffer(numU32sForNextBuffer);
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}
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}
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}
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void GX2Flush()
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{
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GX2Command_Flush(256, true);
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}
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uint64 GX2GetLastSubmittedTimeStamp()
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{
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stdx::atomic_ref<uint64be> _lastSubmissionTime(s_commandState->lastSubmissionTime);
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return _lastSubmissionTime.load();
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}
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uint64 GX2GetRetiredTimeStamp()
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{
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uint64be ts = 0;
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TCL::TCLTimestamp(TCL::TCLTimestampId::TIMESTAMP_LAST_BUFFER_RETIRED, &ts);
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return ts;
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}
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bool GX2WaitTimeStamp(uint64 tsWait)
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{
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// handle GPU timeout here? But for now we timeout after 60 seconds
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TCL::TCLWaitTimestamp(TCL::TCLTimestampId::TIMESTAMP_LAST_BUFFER_RETIRED, tsWait, Espresso::TIMER_CLOCK * 60);
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return true;
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}
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/*
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* Guarantees that the requested amount of space is available on the current command buffer
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* If the space is not available, the current command buffer is pushed to the GPU and a new one is allocated
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*/
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void GX2ReserveCmdSpace(uint32 reservedFreeSpaceInU32)
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{
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uint32 coreIndex = coreinit::OSGetCoreId();
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auto& coreCBState = s_perCoreCBState[coreIndex];
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if (coreCBState.currentWritePtr == nullptr)
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return;
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uint32 writeDistance = (uint32)(coreCBState.currentWritePtr - coreCBState.bufferPtr);
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if (writeDistance + reservedFreeSpaceInU32 > coreCBState.bufferSizeInU32s)
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{
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GX2Command_Flush(reservedFreeSpaceInU32, true);
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}
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gx2WriteGatherCurrentMainCoreIndex = sGX2MainCoreIndex;
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gx2WriteGatherInited = true;
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}
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void GX2WriteGather_beginDisplayList(PPCInterpreter_t* hCPU, MPTR buffer, uint32 maxSize)
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{
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uint32 coreIndex = PPCInterpreter_getCoreIndex(hCPU);
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gx2WriteGatherPipe.displayListStart[coreIndex] = buffer;
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gx2WriteGatherPipe.displayListMaxSize[coreIndex] = maxSize;
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// set new write gather ptr
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gx2WriteGatherPipe.writeGatherPtrDisplayList[coreIndex] = memory_getPointerFromVirtualOffset(gx2WriteGatherPipe.displayListStart[coreIndex]);
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gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] = &gx2WriteGatherPipe.writeGatherPtrDisplayList[coreIndex];
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if (coreIndex == sGX2MainCoreIndex)
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{
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GX2Command_PadCurrentBuffer();
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cemu_assert_debug(!s_perCoreCBState[coreIndex].isDisplayList);
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s_mainCoreLastCommandState = s_perCoreCBState[coreIndex];
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}
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||||
GX2Command_SetupCoreCommandBuffer(MEMPTR<uint32be>(buffer), maxSize/4, true);
|
||||
}
|
||||
|
||||
uint32 GX2WriteGather_getDisplayListWriteDistance(sint32 coreIndex)
|
||||
{
|
||||
return (uint32)(*gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] - memory_getPointerFromVirtualOffset(gx2WriteGatherPipe.displayListStart[coreIndex]));
|
||||
}
|
||||
|
||||
uint32 GX2WriteGather_getFifoWriteDistance(uint32 coreIndex)
|
||||
{
|
||||
uint32 writeDistance = (uint32)(gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex] - gx2WriteGatherPipe.gxRingBuffer);
|
||||
return writeDistance;
|
||||
auto& coreCBState = s_perCoreCBState[coreIndex];
|
||||
cemu_assert_debug(coreCBState.isDisplayList);
|
||||
if (coreCBState.currentWritePtr == nullptr)
|
||||
return 0;
|
||||
return (uint32)(coreCBState.currentWritePtr - coreCBState.bufferPtr) * 4;
|
||||
}
|
||||
|
||||
uint32 GX2WriteGather_endDisplayList(PPCInterpreter_t* hCPU, MPTR buffer)
|
||||
{
|
||||
uint32 coreIndex = PPCInterpreter_getCoreIndex(hCPU);
|
||||
if (gx2WriteGatherPipe.displayListStart[coreIndex] != MPTR_NULL)
|
||||
uint32 coreIndex = coreinit::OSGetCoreId();
|
||||
auto& coreCBState = s_perCoreCBState[coreIndex];
|
||||
GX2Command_PadCurrentBuffer();
|
||||
uint32 finalWriteIndex = coreCBState.currentWritePtr - coreCBState.bufferPtr;
|
||||
cemu_assert_debug(finalWriteIndex <= coreCBState.bufferSizeInU32s);
|
||||
// if we are on the main GX2 core then restore the GPU command buffer
|
||||
if (coreIndex == sGX2MainCoreIndex)
|
||||
{
|
||||
uint32 currentWriteSize = GX2WriteGather_getDisplayListWriteDistance(coreIndex);
|
||||
// pad to 32 byte
|
||||
if (gx2WriteGatherPipe.displayListMaxSize[coreIndex] >= ((gx2WriteGatherPipe.displayListMaxSize[coreIndex] + 0x1F) & ~0x1F))
|
||||
{
|
||||
while ((currentWriteSize & 0x1F) != 0)
|
||||
{
|
||||
gx2WriteGather_submitU32AsBE(pm4HeaderType2Filler());
|
||||
currentWriteSize += 4;
|
||||
}
|
||||
}
|
||||
// get size of written data
|
||||
currentWriteSize = GX2WriteGather_getDisplayListWriteDistance(coreIndex);
|
||||
// disable current display list and restore write gather ptr
|
||||
gx2WriteGatherPipe.displayListStart[coreIndex] = MPTR_NULL;
|
||||
if (sGX2MainCoreIndex == coreIndex)
|
||||
gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] = &gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex];
|
||||
else
|
||||
gx2WriteGatherPipe.writeGatherPtrWrite[coreIndex] = NULL;
|
||||
// return size of (written) display list
|
||||
return currentWriteSize;
|
||||
coreCBState = s_mainCoreLastCommandState;
|
||||
}
|
||||
else
|
||||
{
|
||||
// no active display list
|
||||
// return a size of 0
|
||||
return 0;
|
||||
coreCBState.bufferPtr = nullptr;
|
||||
coreCBState.currentWritePtr = nullptr;
|
||||
coreCBState.bufferSizeInU32s = 0;
|
||||
coreCBState.isDisplayList = false;
|
||||
}
|
||||
return finalWriteIndex * 4;
|
||||
}
|
||||
|
||||
bool GX2GetCurrentDisplayList(betype<MPTR>* displayListAddr, uint32be* displayListSize)
|
||||
bool GX2GetCurrentDisplayList(MEMPTR<uint32be>* displayListAddr, uint32be* displayListSize)
|
||||
{
|
||||
uint32 coreIndex = coreinit::OSGetCoreId();
|
||||
if (gx2WriteGatherPipe.displayListStart[coreIndex] == MPTR_NULL)
|
||||
auto& coreCBState = s_perCoreCBState[coreIndex];
|
||||
if (!coreCBState.isDisplayList)
|
||||
return false;
|
||||
|
||||
if (displayListAddr)
|
||||
*displayListAddr = gx2WriteGatherPipe.displayListStart[coreIndex];
|
||||
*displayListAddr = coreCBState.bufferPtr;
|
||||
if (displayListSize)
|
||||
*displayListSize = gx2WriteGatherPipe.displayListMaxSize[coreIndex];
|
||||
|
||||
*displayListSize = coreCBState.bufferSizeInU32s * sizeof(uint32be);
|
||||
return true;
|
||||
}
|
||||
|
||||
// returns true if we are writing to a display list
|
||||
bool GX2GetDisplayListWriteStatus()
|
||||
{
|
||||
// returns true if we are writing to a display list
|
||||
uint32 coreIndex = coreinit::OSGetCoreId();
|
||||
return gx2WriteGatherPipe.displayListStart[coreIndex] != MPTR_NULL;
|
||||
}
|
||||
|
||||
uint32 GX2WriteGather_getReadWriteDistance()
|
||||
{
|
||||
uint32 coreIndex = sGX2MainCoreIndex;
|
||||
uint32 writeDistance = (uint32)(gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex] + GX2_COMMAND_RING_BUFFER_SIZE - gxRingBufferReadPtr);
|
||||
writeDistance %= GX2_COMMAND_RING_BUFFER_SIZE;
|
||||
return writeDistance;
|
||||
}
|
||||
|
||||
void GX2WriteGather_checkAndInsertWrapAroundMark()
|
||||
{
|
||||
uint32 coreIndex = coreinit::OSGetCoreId();
|
||||
if (coreIndex != sGX2MainCoreIndex) // only if main gx2 core
|
||||
return;
|
||||
if (gx2WriteGatherPipe.displayListStart[coreIndex] != MPTR_NULL)
|
||||
return;
|
||||
uint32 writeDistance = GX2WriteGather_getFifoWriteDistance(coreIndex);
|
||||
if (writeDistance >= (GX2_COMMAND_RING_BUFFER_SIZE * 3 / 5))
|
||||
{
|
||||
gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_HLE_FIFO_WRAP_AROUND, 1));
|
||||
gx2WriteGather_submitU32AsBE(0); // empty word since we can't send commands with zero data words
|
||||
gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex] = gx2WriteGatherPipe.gxRingBuffer;
|
||||
}
|
||||
return s_perCoreCBState[coreIndex].isDisplayList;
|
||||
}
|
||||
|
||||
void GX2BeginDisplayList(MEMPTR<void> displayListAddr, uint32 size)
|
||||
|
|
@ -204,28 +423,23 @@ namespace GX2
|
|||
memory_virtualToPhysical(addr),
|
||||
0, // high address bits
|
||||
size / 4);
|
||||
GX2::GX2WriteGather_checkAndInsertWrapAroundMark();
|
||||
}
|
||||
|
||||
void GX2DirectCallDisplayList(void* addr, uint32 size)
|
||||
{
|
||||
// this API submits to TCL directly and bypasses write-gatherer
|
||||
// its basically a way to manually submit a command buffer to the GPU
|
||||
// as such it also affects the submission and retire timestamps
|
||||
|
||||
uint32 coreIndex = PPCInterpreter_getCoreIndex(PPCInterpreter_getCurrentInstance());
|
||||
cemu_assert_debug(coreIndex == sGX2MainCoreIndex);
|
||||
coreIndex = sGX2MainCoreIndex; // always submit to main queue which is owned by GX2 main core (TCLSubmitToRing does not need this workaround)
|
||||
|
||||
uint32be* cmdStream = (uint32be*)(gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex]);
|
||||
cmdStream[0] = pm4HeaderType3(IT_INDIRECT_BUFFER_PRIV, 3);
|
||||
cmdStream[1] = memory_virtualToPhysical(MEMPTR<void>(addr).GetMPTR());
|
||||
cmdStream[2] = 0;
|
||||
cmdStream[3] = size / 4;
|
||||
gx2WriteGatherPipe.writeGatherPtrGxBuffer[coreIndex] += 16;
|
||||
|
||||
// update submission timestamp and retired timestamp
|
||||
_GX2SubmitToTCL();
|
||||
uint32 coreIndex = coreinit::OSGetCoreId();
|
||||
if (coreIndex != sGX2MainCoreIndex)
|
||||
{
|
||||
cemuLog_logDebugOnce(LogType::Force, "GX2DirectCallDisplayList() called on non-main GX2 core");
|
||||
}
|
||||
if (!s_perCoreCBState[coreIndex].isDisplayList)
|
||||
{
|
||||
// make sure any preceeding commands are submitted first
|
||||
GX2Command_Flush(0x100, false);
|
||||
}
|
||||
GX2Command_SubmitCommandBuffer(static_cast<uint32be*>(addr), size / 4, nullptr, false);
|
||||
}
|
||||
|
||||
void GX2CopyDisplayList(MEMPTR<uint32be*> addr, uint32 size)
|
||||
|
|
@ -288,6 +502,12 @@ namespace GX2
|
|||
|
||||
void GX2CommandInit()
|
||||
{
|
||||
cafeExportRegister("gx2", GX2Flush, LogType::GX2);
|
||||
|
||||
cafeExportRegister("gx2", GX2GetLastSubmittedTimeStamp, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2GetRetiredTimeStamp, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2WaitTimeStamp, LogType::GX2);
|
||||
|
||||
cafeExportRegister("gx2", GX2BeginDisplayList, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2BeginDisplayListEx, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2EndDisplayList, LogType::GX2);
|
||||
|
|
@ -295,7 +515,6 @@ namespace GX2
|
|||
cafeExportRegister("gx2", GX2GetCurrentDisplayList, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2GetDisplayListWriteStatus, LogType::GX2);
|
||||
|
||||
|
||||
cafeExportRegister("gx2", GX2CallDisplayList, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2DirectCallDisplayList, LogType::GX2);
|
||||
cafeExportRegister("gx2", GX2CopyDisplayList, LogType::GX2);
|
||||
|
|
@ -305,7 +524,10 @@ namespace GX2
|
|||
|
||||
void GX2CommandResetToDefaultState()
|
||||
{
|
||||
GX2WriteGather_ResetToDefaultState();
|
||||
s_commandState->commandPoolBase = nullptr;
|
||||
s_commandState->commandPoolSizeInU32s = 0;
|
||||
s_commandState->gpuCommandReadPtr = nullptr;
|
||||
s_cbBufferIsInternallyAllocated = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue