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https://github.com/cemu-project/Cemu.git
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create helper function for rasterization kill
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05518c01fb
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5 changed files with 37 additions and 65 deletions
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@ -9,6 +9,7 @@
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#include "Cafe/HW/Latte/Renderer/Vulkan/VulkanRenderer.h"
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#include "Cafe/HW/Latte/Renderer/Vulkan/VulkanRenderer.h"
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#include "Cafe/OS/libs/gx2/GX2.h" // todo - remove dependency
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#include "Cafe/OS/libs/gx2/GX2.h" // todo - remove dependency
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#include "Cafe/GraphicPack/GraphicPack2.h"
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#include "Cafe/GraphicPack/GraphicPack2.h"
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#include "HW/Latte/Core/Latte.h"
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#include "HW/Latte/Renderer/Renderer.h"
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#include "HW/Latte/Renderer/Renderer.h"
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#include "util/helpers/StringParser.h"
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#include "util/helpers/StringParser.h"
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#include "config/ActiveSettings.h"
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#include "config/ActiveSettings.h"
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@ -543,20 +544,7 @@ void LatteSHRC_UpdateVSBaseHash(uint8* vertexShaderPtr, uint32 vertexShaderSize,
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if (!usesGeometryShader)
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if (!usesGeometryShader)
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{
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{
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// Rasterization
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if (LatteGPUState.contextNew.IsRasterizationEnabled())
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bool rasterizationEnabled = !LatteGPUState.contextNew.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
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// HACK
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if (!LatteGPUState.contextNew.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
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rasterizationEnabled = true;
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const auto& polygonControlReg = LatteGPUState.contextNew.PA_SU_SC_MODE_CNTL;
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uint32 cullFront = polygonControlReg.get_CULL_FRONT();
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uint32 cullBack = polygonControlReg.get_CULL_BACK();
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if (cullFront && cullBack)
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rasterizationEnabled = false;
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if (rasterizationEnabled)
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vsHash += 51ULL;
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vsHash += 51ULL;
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// Vertex fetch
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// Vertex fetch
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@ -52,20 +52,20 @@ namespace Latte
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{
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{
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// same as E_TILEMODE but contains additional options with special meaning
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// same as E_TILEMODE but contains additional options with special meaning
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TM_LINEAR_GENERAL = 0,
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TM_LINEAR_GENERAL = 0,
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TM_LINEAR_ALIGNED = 1,
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TM_LINEAR_ALIGNED = 1,
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// micro-tiled
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// micro-tiled
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TM_1D_TILED_THIN1 = 2,
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TM_1D_TILED_THIN1 = 2,
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TM_1D_TILED_THICK = 3,
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TM_1D_TILED_THICK = 3,
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// macro-tiled
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// macro-tiled
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TM_2D_TILED_THIN1 = 4,
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TM_2D_TILED_THIN1 = 4,
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TM_2D_TILED_THIN2 = 5,
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TM_2D_TILED_THIN2 = 5,
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TM_2D_TILED_THIN4 = 6,
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TM_2D_TILED_THIN4 = 6,
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TM_2D_TILED_THICK = 7,
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TM_2D_TILED_THICK = 7,
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TM_2B_TILED_THIN1 = 8,
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TM_2B_TILED_THIN1 = 8,
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TM_2B_TILED_THIN2 = 9,
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TM_2B_TILED_THIN2 = 9,
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TM_2B_TILED_THIN4 = 10,
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TM_2B_TILED_THIN4 = 10,
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TM_2B_TILED_THICK = 11,
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TM_2B_TILED_THICK = 11,
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@ -179,7 +179,7 @@ namespace Latte
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HWFMT_4_4_4_4 = 0xB,
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HWFMT_4_4_4_4 = 0xB,
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HWFMT_5_5_5_1 = 0xC,
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HWFMT_5_5_5_1 = 0xC,
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HWFMT_32 = 0xD,
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HWFMT_32 = 0xD,
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HWFMT_32_FLOAT = 0xE,
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HWFMT_32_FLOAT = 0xE,
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HWFMT_16_16 = 0xF,
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HWFMT_16_16 = 0xF,
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HWFMT_16_16_FLOAT = 0x10,
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HWFMT_16_16_FLOAT = 0x10,
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HWFMT_8_24 = 0x11,
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HWFMT_8_24 = 0x11,
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@ -284,7 +284,7 @@ namespace Latte
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R32_G32_B32_A32_UINT = (HWFMT_32_32_32_32 | FMT_BIT_INT),
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R32_G32_B32_A32_UINT = (HWFMT_32_32_32_32 | FMT_BIT_INT),
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R32_G32_B32_A32_SINT = (HWFMT_32_32_32_32 | FMT_BIT_INT | FMT_BIT_SIGNED),
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R32_G32_B32_A32_SINT = (HWFMT_32_32_32_32 | FMT_BIT_INT | FMT_BIT_SIGNED),
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R32_G32_B32_A32_FLOAT = (HWFMT_32_32_32_32_FLOAT | FMT_BIT_FLOAT),
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R32_G32_B32_A32_FLOAT = (HWFMT_32_32_32_32_FLOAT | FMT_BIT_FLOAT),
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// depth
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// depth
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D24_S8_UNORM = (HWFMT_8_24),
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D24_S8_UNORM = (HWFMT_8_24),
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D24_S8_FLOAT = (HWFMT_8_24 | FMT_BIT_FLOAT),
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D24_S8_FLOAT = (HWFMT_8_24 | FMT_BIT_FLOAT),
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@ -353,7 +353,7 @@ namespace Latte
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enum GPU_LIMITS
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enum GPU_LIMITS
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{
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{
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NUM_VERTEX_BUFFERS = 16,
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NUM_VERTEX_BUFFERS = 16,
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NUM_TEXTURES_PER_STAGE = 18,
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NUM_TEXTURES_PER_STAGE = 18,
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NUM_SAMPLERS_PER_STAGE = 18, // is this 16 or 18?
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NUM_SAMPLERS_PER_STAGE = 18, // is this 16 or 18?
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NUM_COLOR_ATTACHMENTS = 8,
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NUM_COLOR_ATTACHMENTS = 8,
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};
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};
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@ -1579,7 +1579,7 @@ struct LatteContextRegister
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/* +0x3A4C0 */ _LatteRegisterSetTextureUnit SQ_TEX_START_GS[Latte::GPU_LIMITS::NUM_TEXTURES_PER_STAGE];
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/* +0x3A4C0 */ _LatteRegisterSetTextureUnit SQ_TEX_START_GS[Latte::GPU_LIMITS::NUM_TEXTURES_PER_STAGE];
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uint8 padding_3A6B8[0x3C000 - 0x3A6B8];
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uint8 padding_3A6B8[0x3C000 - 0x3A6B8];
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/* +0x3C000 */ _LatteRegisterSetSampler SQ_TEX_SAMPLER[18 * 3];
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/* +0x3C000 */ _LatteRegisterSetSampler SQ_TEX_SAMPLER[18 * 3];
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/* +0x3C288 */
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/* +0x3C288 */
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@ -1598,6 +1598,24 @@ struct LatteContextRegister
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{
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{
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return (uint32*)hleSpecialState;
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return (uint32*)hleSpecialState;
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}
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}
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bool IsRasterizationEnabled() const
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{
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bool rasterizationEnabled = !PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
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// GX2SetSpecialState(0, true) enables DX_RASTERIZATION_KILL, but still expects depth writes to happen? -> Research which stages are disabled by DX_RASTERIZATION_KILL exactly
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// for now we use a workaround:
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if (!PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
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rasterizationEnabled = true;
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// Culling both front and back faces effectively disables rasterization
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uint32 cullFront = PA_SU_SC_MODE_CNTL.get_CULL_FRONT();
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uint32 cullBack = PA_SU_SC_MODE_CNTL.get_CULL_BACK();
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if (cullFront && cullBack)
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rasterizationEnabled = false;
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return rasterizationEnabled;
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}
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};
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};
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static_assert(sizeof(LatteContextRegister) == 0x10000 * 4 + 9 * 4);
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static_assert(sizeof(LatteContextRegister) == 0x10000 * 4 + 9 * 4);
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@ -1664,4 +1682,4 @@ static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_ES) == Latte::REGA
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static_assert(offsetof(LatteContextRegister, SQ_PGM_START_GS) == Latte::REGADDR::SQ_PGM_START_GS * 4);
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static_assert(offsetof(LatteContextRegister, SQ_PGM_START_GS) == Latte::REGADDR::SQ_PGM_START_GS * 4);
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static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_GS) == Latte::REGADDR::SQ_PGM_RESOURCES_GS * 4);
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static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_GS) == Latte::REGADDR::SQ_PGM_RESOURCES_GS * 4);
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static_assert(offsetof(LatteContextRegister, SPI_VS_OUT_CONFIG) == Latte::REGADDR::SPI_VS_OUT_CONFIG * 4);
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static_assert(offsetof(LatteContextRegister, SPI_VS_OUT_CONFIG) == Latte::REGADDR::SPI_VS_OUT_CONFIG * 4);
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static_assert(offsetof(LatteContextRegister, LATTE_SPI_VS_OUT_ID_N) == Latte::REGADDR::SPI_VS_OUT_ID_0 * 4);
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static_assert(offsetof(LatteContextRegister, LATTE_SPI_VS_OUT_ID_N) == Latte::REGADDR::SPI_VS_OUT_ID_0 * 4);
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@ -3938,21 +3938,7 @@ void LatteDecompiler_emitMSLShader(LatteDecompilerShaderContext* shaderContext,
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bool fetchVertexManually = (usesGeometryShader || (shaderContext->fetchShader && shaderContext->fetchShader->mtlFetchVertexManually));
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bool fetchVertexManually = (usesGeometryShader || (shaderContext->fetchShader && shaderContext->fetchShader->mtlFetchVertexManually));
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// Rasterization
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// Rasterization
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rasterizationEnabled = true;
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rasterizationEnabled = shaderContext->contextRegistersNew->IsRasterizationEnabled();
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if (shader->shaderType == LatteConst::ShaderType::Vertex && !usesGeometryShader)
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{
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rasterizationEnabled = !shaderContext->contextRegistersNew->PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
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// HACK
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if (!shaderContext->contextRegistersNew->PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
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rasterizationEnabled = true;
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const auto& polygonControlReg = shaderContext->contextRegistersNew->PA_SU_SC_MODE_CNTL;
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uint32 cullFront = polygonControlReg.get_CULL_FRONT();
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uint32 cullBack = polygonControlReg.get_CULL_BACK();
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if (cullFront && cullBack)
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rasterizationEnabled = false;
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}
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StringBuf* src = new StringBuf(1024*1024*12); // reserve 12MB for generated source (we resize-to-fit at the end)
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StringBuf* src = new StringBuf(1024*1024*12); // reserve 12MB for generated source (we resize-to-fit at the end)
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shaderContext->shaderSource = src;
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shaderContext->shaderSource = src;
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@ -295,19 +295,7 @@ void MetalPipelineCompiler::InitFromState(const LatteFetchShader* fetchShader, c
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m_usesGeometryShader = (geometryShader != nullptr || isPrimitiveRect);
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m_usesGeometryShader = (geometryShader != nullptr || isPrimitiveRect);
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// Rasterization
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// Rasterization
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m_rasterizationEnabled = !lcr.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
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m_rasterizationEnabled = lcr.IsRasterizationEnabled();
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// HACK
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// TODO: include this in the hash?
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if (!lcr.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
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m_rasterizationEnabled = true;
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// Culling both front and back faces effectively disables rasterization
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const auto& polygonControlReg = lcr.PA_SU_SC_MODE_CNTL;
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uint32 cullFront = polygonControlReg.get_CULL_FRONT();
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uint32 cullBack = polygonControlReg.get_CULL_BACK();
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if (cullFront && cullBack)
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m_rasterizationEnabled = false;
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// Shaders
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// Shaders
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m_vertexShaderMtl = static_cast<RendererShaderMtl*>(vertexShader->shader);
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m_vertexShaderMtl = static_cast<RendererShaderMtl*>(vertexShader->shader);
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@ -1065,15 +1065,7 @@ void MetalRenderer::draw_beginSequence()
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LatteRenderTarget_updateViewport();
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LatteRenderTarget_updateViewport();
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LatteRenderTarget_updateScissorBox();
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LatteRenderTarget_updateScissorBox();
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// check for conditions which would turn the drawcalls into no-ops
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if (!LatteGPUState.contextNew.IsRasterizationEnabled() && !streamoutEnable)
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bool rasterizerEnable = !LatteGPUState.contextNew.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
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// GX2SetSpecialState(0, true) enables DX_RASTERIZATION_KILL, but still expects depth writes to happen? -> Research which stages are disabled by DX_RASTERIZATION_KILL exactly
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// for now we use a workaround:
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if (!LatteGPUState.contextNew.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
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rasterizerEnable = true;
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if (!rasterizerEnable && !streamoutEnable)
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m_state.m_skipDrawSequence = true;
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m_state.m_skipDrawSequence = true;
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}
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}
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