create helper function for rasterization kill

This commit is contained in:
Samuliak 2025-01-28 16:41:30 +01:00
parent 05518c01fb
commit 1fb9cfd783
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5 changed files with 37 additions and 65 deletions

View file

@ -9,6 +9,7 @@
#include "Cafe/HW/Latte/Renderer/Vulkan/VulkanRenderer.h" #include "Cafe/HW/Latte/Renderer/Vulkan/VulkanRenderer.h"
#include "Cafe/OS/libs/gx2/GX2.h" // todo - remove dependency #include "Cafe/OS/libs/gx2/GX2.h" // todo - remove dependency
#include "Cafe/GraphicPack/GraphicPack2.h" #include "Cafe/GraphicPack/GraphicPack2.h"
#include "HW/Latte/Core/Latte.h"
#include "HW/Latte/Renderer/Renderer.h" #include "HW/Latte/Renderer/Renderer.h"
#include "util/helpers/StringParser.h" #include "util/helpers/StringParser.h"
#include "config/ActiveSettings.h" #include "config/ActiveSettings.h"
@ -543,20 +544,7 @@ void LatteSHRC_UpdateVSBaseHash(uint8* vertexShaderPtr, uint32 vertexShaderSize,
if (!usesGeometryShader) if (!usesGeometryShader)
{ {
// Rasterization if (LatteGPUState.contextNew.IsRasterizationEnabled())
bool rasterizationEnabled = !LatteGPUState.contextNew.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
// HACK
if (!LatteGPUState.contextNew.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
rasterizationEnabled = true;
const auto& polygonControlReg = LatteGPUState.contextNew.PA_SU_SC_MODE_CNTL;
uint32 cullFront = polygonControlReg.get_CULL_FRONT();
uint32 cullBack = polygonControlReg.get_CULL_BACK();
if (cullFront && cullBack)
rasterizationEnabled = false;
if (rasterizationEnabled)
vsHash += 51ULL; vsHash += 51ULL;
// Vertex fetch // Vertex fetch

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@ -52,20 +52,20 @@ namespace Latte
{ {
// same as E_TILEMODE but contains additional options with special meaning // same as E_TILEMODE but contains additional options with special meaning
TM_LINEAR_GENERAL = 0, TM_LINEAR_GENERAL = 0,
TM_LINEAR_ALIGNED = 1, TM_LINEAR_ALIGNED = 1,
// micro-tiled // micro-tiled
TM_1D_TILED_THIN1 = 2, TM_1D_TILED_THIN1 = 2,
TM_1D_TILED_THICK = 3, TM_1D_TILED_THICK = 3,
// macro-tiled // macro-tiled
TM_2D_TILED_THIN1 = 4, TM_2D_TILED_THIN1 = 4,
TM_2D_TILED_THIN2 = 5, TM_2D_TILED_THIN2 = 5,
TM_2D_TILED_THIN4 = 6, TM_2D_TILED_THIN4 = 6,
TM_2D_TILED_THICK = 7, TM_2D_TILED_THICK = 7,
TM_2B_TILED_THIN1 = 8, TM_2B_TILED_THIN1 = 8,
TM_2B_TILED_THIN2 = 9, TM_2B_TILED_THIN2 = 9,
TM_2B_TILED_THIN4 = 10, TM_2B_TILED_THIN4 = 10,
TM_2B_TILED_THICK = 11, TM_2B_TILED_THICK = 11,
@ -179,7 +179,7 @@ namespace Latte
HWFMT_4_4_4_4 = 0xB, HWFMT_4_4_4_4 = 0xB,
HWFMT_5_5_5_1 = 0xC, HWFMT_5_5_5_1 = 0xC,
HWFMT_32 = 0xD, HWFMT_32 = 0xD,
HWFMT_32_FLOAT = 0xE, HWFMT_32_FLOAT = 0xE,
HWFMT_16_16 = 0xF, HWFMT_16_16 = 0xF,
HWFMT_16_16_FLOAT = 0x10, HWFMT_16_16_FLOAT = 0x10,
HWFMT_8_24 = 0x11, HWFMT_8_24 = 0x11,
@ -284,7 +284,7 @@ namespace Latte
R32_G32_B32_A32_UINT = (HWFMT_32_32_32_32 | FMT_BIT_INT), R32_G32_B32_A32_UINT = (HWFMT_32_32_32_32 | FMT_BIT_INT),
R32_G32_B32_A32_SINT = (HWFMT_32_32_32_32 | FMT_BIT_INT | FMT_BIT_SIGNED), R32_G32_B32_A32_SINT = (HWFMT_32_32_32_32 | FMT_BIT_INT | FMT_BIT_SIGNED),
R32_G32_B32_A32_FLOAT = (HWFMT_32_32_32_32_FLOAT | FMT_BIT_FLOAT), R32_G32_B32_A32_FLOAT = (HWFMT_32_32_32_32_FLOAT | FMT_BIT_FLOAT),
// depth // depth
D24_S8_UNORM = (HWFMT_8_24), D24_S8_UNORM = (HWFMT_8_24),
D24_S8_FLOAT = (HWFMT_8_24 | FMT_BIT_FLOAT), D24_S8_FLOAT = (HWFMT_8_24 | FMT_BIT_FLOAT),
@ -353,7 +353,7 @@ namespace Latte
enum GPU_LIMITS enum GPU_LIMITS
{ {
NUM_VERTEX_BUFFERS = 16, NUM_VERTEX_BUFFERS = 16,
NUM_TEXTURES_PER_STAGE = 18, NUM_TEXTURES_PER_STAGE = 18,
NUM_SAMPLERS_PER_STAGE = 18, // is this 16 or 18? NUM_SAMPLERS_PER_STAGE = 18, // is this 16 or 18?
NUM_COLOR_ATTACHMENTS = 8, NUM_COLOR_ATTACHMENTS = 8,
}; };
@ -1579,7 +1579,7 @@ struct LatteContextRegister
/* +0x3A4C0 */ _LatteRegisterSetTextureUnit SQ_TEX_START_GS[Latte::GPU_LIMITS::NUM_TEXTURES_PER_STAGE]; /* +0x3A4C0 */ _LatteRegisterSetTextureUnit SQ_TEX_START_GS[Latte::GPU_LIMITS::NUM_TEXTURES_PER_STAGE];
uint8 padding_3A6B8[0x3C000 - 0x3A6B8]; uint8 padding_3A6B8[0x3C000 - 0x3A6B8];
/* +0x3C000 */ _LatteRegisterSetSampler SQ_TEX_SAMPLER[18 * 3]; /* +0x3C000 */ _LatteRegisterSetSampler SQ_TEX_SAMPLER[18 * 3];
/* +0x3C288 */ /* +0x3C288 */
@ -1598,6 +1598,24 @@ struct LatteContextRegister
{ {
return (uint32*)hleSpecialState; return (uint32*)hleSpecialState;
} }
bool IsRasterizationEnabled() const
{
bool rasterizationEnabled = !PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
// GX2SetSpecialState(0, true) enables DX_RASTERIZATION_KILL, but still expects depth writes to happen? -> Research which stages are disabled by DX_RASTERIZATION_KILL exactly
// for now we use a workaround:
if (!PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
rasterizationEnabled = true;
// Culling both front and back faces effectively disables rasterization
uint32 cullFront = PA_SU_SC_MODE_CNTL.get_CULL_FRONT();
uint32 cullBack = PA_SU_SC_MODE_CNTL.get_CULL_BACK();
if (cullFront && cullBack)
rasterizationEnabled = false;
return rasterizationEnabled;
}
}; };
static_assert(sizeof(LatteContextRegister) == 0x10000 * 4 + 9 * 4); static_assert(sizeof(LatteContextRegister) == 0x10000 * 4 + 9 * 4);
@ -1664,4 +1682,4 @@ static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_ES) == Latte::REGA
static_assert(offsetof(LatteContextRegister, SQ_PGM_START_GS) == Latte::REGADDR::SQ_PGM_START_GS * 4); static_assert(offsetof(LatteContextRegister, SQ_PGM_START_GS) == Latte::REGADDR::SQ_PGM_START_GS * 4);
static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_GS) == Latte::REGADDR::SQ_PGM_RESOURCES_GS * 4); static_assert(offsetof(LatteContextRegister, SQ_PGM_RESOURCES_GS) == Latte::REGADDR::SQ_PGM_RESOURCES_GS * 4);
static_assert(offsetof(LatteContextRegister, SPI_VS_OUT_CONFIG) == Latte::REGADDR::SPI_VS_OUT_CONFIG * 4); static_assert(offsetof(LatteContextRegister, SPI_VS_OUT_CONFIG) == Latte::REGADDR::SPI_VS_OUT_CONFIG * 4);
static_assert(offsetof(LatteContextRegister, LATTE_SPI_VS_OUT_ID_N) == Latte::REGADDR::SPI_VS_OUT_ID_0 * 4); static_assert(offsetof(LatteContextRegister, LATTE_SPI_VS_OUT_ID_N) == Latte::REGADDR::SPI_VS_OUT_ID_0 * 4);

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@ -3938,21 +3938,7 @@ void LatteDecompiler_emitMSLShader(LatteDecompilerShaderContext* shaderContext,
bool fetchVertexManually = (usesGeometryShader || (shaderContext->fetchShader && shaderContext->fetchShader->mtlFetchVertexManually)); bool fetchVertexManually = (usesGeometryShader || (shaderContext->fetchShader && shaderContext->fetchShader->mtlFetchVertexManually));
// Rasterization // Rasterization
rasterizationEnabled = true; rasterizationEnabled = shaderContext->contextRegistersNew->IsRasterizationEnabled();
if (shader->shaderType == LatteConst::ShaderType::Vertex && !usesGeometryShader)
{
rasterizationEnabled = !shaderContext->contextRegistersNew->PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
// HACK
if (!shaderContext->contextRegistersNew->PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
rasterizationEnabled = true;
const auto& polygonControlReg = shaderContext->contextRegistersNew->PA_SU_SC_MODE_CNTL;
uint32 cullFront = polygonControlReg.get_CULL_FRONT();
uint32 cullBack = polygonControlReg.get_CULL_BACK();
if (cullFront && cullBack)
rasterizationEnabled = false;
}
StringBuf* src = new StringBuf(1024*1024*12); // reserve 12MB for generated source (we resize-to-fit at the end) StringBuf* src = new StringBuf(1024*1024*12); // reserve 12MB for generated source (we resize-to-fit at the end)
shaderContext->shaderSource = src; shaderContext->shaderSource = src;

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@ -295,19 +295,7 @@ void MetalPipelineCompiler::InitFromState(const LatteFetchShader* fetchShader, c
m_usesGeometryShader = (geometryShader != nullptr || isPrimitiveRect); m_usesGeometryShader = (geometryShader != nullptr || isPrimitiveRect);
// Rasterization // Rasterization
m_rasterizationEnabled = !lcr.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL(); m_rasterizationEnabled = lcr.IsRasterizationEnabled();
// HACK
// TODO: include this in the hash?
if (!lcr.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
m_rasterizationEnabled = true;
// Culling both front and back faces effectively disables rasterization
const auto& polygonControlReg = lcr.PA_SU_SC_MODE_CNTL;
uint32 cullFront = polygonControlReg.get_CULL_FRONT();
uint32 cullBack = polygonControlReg.get_CULL_BACK();
if (cullFront && cullBack)
m_rasterizationEnabled = false;
// Shaders // Shaders
m_vertexShaderMtl = static_cast<RendererShaderMtl*>(vertexShader->shader); m_vertexShaderMtl = static_cast<RendererShaderMtl*>(vertexShader->shader);

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@ -1065,15 +1065,7 @@ void MetalRenderer::draw_beginSequence()
LatteRenderTarget_updateViewport(); LatteRenderTarget_updateViewport();
LatteRenderTarget_updateScissorBox(); LatteRenderTarget_updateScissorBox();
// check for conditions which would turn the drawcalls into no-ops if (!LatteGPUState.contextNew.IsRasterizationEnabled() && !streamoutEnable)
bool rasterizerEnable = !LatteGPUState.contextNew.PA_CL_CLIP_CNTL.get_DX_RASTERIZATION_KILL();
// GX2SetSpecialState(0, true) enables DX_RASTERIZATION_KILL, but still expects depth writes to happen? -> Research which stages are disabled by DX_RASTERIZATION_KILL exactly
// for now we use a workaround:
if (!LatteGPUState.contextNew.PA_CL_VTE_CNTL.get_VPORT_X_OFFSET_ENA())
rasterizerEnable = true;
if (!rasterizerEnable && !streamoutEnable)
m_state.m_skipDrawSequence = true; m_state.m_skipDrawSequence = true;
} }